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TMS320C6678: RapidIO to a Cyclone IV fpga

Part Number: TMS320C6678

Dear Mr./Ms.,

Cyclone IV GX fpga's RapidIO IP core runs as a slave with a DSP 6678, direct connect.

Run in 1X mode , 2.5GHz.

In FPGA qsys, rapidio ip core has only io_write_master and io_read_master connecting to a DPRAM. No cpu, no Nios.

Now, Port_OK while fpga get no io_m_wr_write or io_m__rd_read signal when DSP NWRITE/NREAD/SWRITE.

DSP side can sucessfully write and read by rapidio in internal loop mode.

Could you please give me some suggestion on how to debug it?

Thank you.

  • Hi,

    I am sorry I couldn't understand the question. Is it that you cannot establish proper connection between DSP and FPGA?

    Also please elaborate on which Processor SDK RTOS version are you using?

    Best Regards,
    Yordan

     


     Please make sure you read the forum guidelines first.

  • In reply to Yordan Kovachev:

    Hi Yordan,

    Yes, I cannot establish the proper connection.

    I downloaded and installed SDK as: C:\ti\pdk_c667x_2_0_10\packages\ti\drv\srio

    Actually, RTOS will not be used in my design. Is there any simplified sample code to refer?

    Thank you.
    Peijun
  • In reply to Peijun Zhu:

    Hi Peijun,

    You can refer to the PDK SRIO examples (the srio settings are located in the directory above: C:\ti\pdk_c667x_2_0_10\packages\ti\drv\srio). Srio examples documentation is located here:
    software-dl.ti.com/.../Device_Drivers.html

    Also there is a document in: /ti/pdk_c667x_x_x_x/packages/ti/drv/srio/test/tput_benchmarking/docs.

    This is the reference code we have.

    Best Regards,
    Yordan

     


     Please make sure you read the forum guidelines first.

  • In reply to Yordan Kovachev:

    Hi Yordan,

    Problem solved. It is on FPGA configuration.

  • Hello, will be doing the same on my design using a Cyclone V. Would you be willing to share you FPGA design?

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