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AM5K2E04: Boot Up Duration from Reset to U-Boot

Prodigy 160 points

Replies: 35

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Part Number: AM5K2E04

Hello,

 

Analyzing the boot procedure of a TI AM5K2E04 we tumbled over an unexpectedly long period of time between the end of the reset sequence and the entrance of U-Boot.

BOOTCOMPLETE pin is used to indicate the beginning of U-Boot function board_init_f(), where we set the BOOTCOMPLETE register at address 0x0262013C to 0xFFFFFFFF to generate a rising edge of BOOTCOMPLETE pin (pin AF31).

Between the end of the reset (rising edge of RESETSTAT#, pin AH29) and the entrance of board_init_f() a duration as long as 560 ms elapses (measured with oscilloscope). We can't explain this timespan to ourselves, as we for example expect a duration of about 60 ms to copy the U-Boot (about 150 kB in size); we are using EMIF Boot mode.

Is it plausible that almost 600 ms elapse from the end of reset to the entrance of board_init_f()? What’s going on during this time?

 

Thanks, best regards

Lennart

  • In reply to Mukul Bhatnagar:

    Gerald, Lennart,

    Additional update on this issue. We had a internal discussion on this topic where we reviewed the information obtained from you. It appears that in one of the E2E threads where you have shared the scope shots, you are reading the SYSCLK/6 to be 16.67 MHz initially when the PLL is in bypass state . Our understanding earlier was that the SYSCLK on your custom board is 312.5 MHz can you indicate why the scope seems to suggest that the clock is 100 MHz.

    If the SYSCLK is indeed 100 Mhz then your observation seems to be consistent with our benchmark of 42 million cycles in ROM before PLL is configured for EMIF NAND boot. This will result in a delay of about ~420 ms  (measured is ~450 ms in your scope shot). Please clarify if the clock on your custom board is 100 Mhz or 312.5 Mhz.

    Regards,

    Rahul

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  • In reply to Rahul Prabhu:

    Hello Rahul,

    yes, as we wrote our external clock runs with a frequency of 100 MHz. For testing purposes we switched to 312.5 MHz and could observe that the delay shrunk from 460 ms to 147 ms (which is exactly 460 ms * 100 MHz / 312,5 MHz) and matches your findings that the PLL needs about 42E6 cycles to come up.

    Now that this "mysterious phase" seems to be identified as the initialization of the PLL, a major question still persists:

    Is there any chance to speed this up (apart from the higher clock)? Maybe by using another device type?

    And could you please provide information about the correlation of the reset signals (RESET#, POR#, RESETFULL#) and the behavior of the PLL? In other words: if we do not release all three resets more or less at the same time (delayed by 100 µs) as we do currently, is there any possibility to start the PLL configuration at an earlier point in time and trigger the actual boot procedure separately?

    Best regards

    Lennart

  • In reply to Lennart Siekmann:

    Lennart,

    Thanks for confirming my observations from the EVM with your setup so it does appear that the time taken until ROM configures the PLL is the root cause for the failure. As far as ROM code is concerned, we can`t modify this chip behavior.

    I will let our hardware experts provide their inputs on the power sequencing question as this is not my area of expertise.

    Regards,

    Rahul

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  • In reply to Rahul Prabhu:

    Hi Rahul,

    are there any news concerning the reset sequence?

    Best regards

    Lennart

  • In reply to Lennart Siekmann:

    Lennart,

    There appears to be some misunderstanding.  The delay of 42e6 cycles that you and Rahul have both measured is the delay from start of BOOTROM execution to the point where the PLL has been reconfigured.  This is not a reset hardware logic delay or a PLL reconfiguration and lock delay.  These hardware delays are very short (<1ms).  The delay of 42e6 cycles is a BOOTROM execution delay that cannot be shortened.  However, as you have validated, this fixed cycle delay can be minimized by increasing the BYPASS clock rate to the maximum allowed rate of 312.5MHz.  This cycle delay is same for all K2E devices.

    Tom