Part Number: AM3352
I am apply the tuning the DDR3 Timings for a new design based on the http://processors.wiki.ti.com/index.php/Sitara_Linux_Training:_Tuning_the_DDR3_Timings_on_BeagleBoneBlack wiki.
All works fine up to running the Scripts->AM335x DDR Tests->EDMA. here I get error.
Could anybody give me some tip to help find root cause?
As attachment the EDMA test log and my Gel file.
Sébastienam3352 303MHz - with new CCS value board 12.gelam3352 400MHz - with new CCS value board 12.geledma_log.txt
In reply to Seb O:
Sebastien, it doesn't look like you copied over the "EMIF parameters" portion from the spreadsheet to the GEL file. Please copy over all of the "GEL" tab contents and use it to replace the similar lines in the GEL.
I'm not sure why you are not getting "PHY is ready" message. You may want to try using some of the GELs that come with the CCS installation (found in ccs_base\emulation\boards)
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In reply to JJD:
In fact I've updated the xlsx file to match my memory PN ISSI IS43TR16128C-15HBLI.
Anyway, I've tryed the value from the orignal xlsx you sent me.
I attach you a screen shot CCS with gel, log and memory dump at test#2 step. I've simplfied the log message to make it more clear to provide this screen shot and display the memories content at 0x8000_0000, 0x4030_0000, 0x4030_0800 and , 0x8000_0800
We can see @ 0x8000 0000 the pattern written in DDR3 during test 2 then the content of internal memory at 0x0403 0000 after DMA transfert
> After this DMA transfert we should get the same as DDR3 in internal RAM. What I get in internal RAM is the pattern of TEST 1!
We can see @ 0x0403 0800 the pattern written in internal memory during test 2 then the content of DDR3 at 0x8000 0800 after DMA transfert
> This DMA transfert is OK
I get the same for test 3 to 8. I don't show to make the screen shot more clear and make the test iteration faster.
I don't understand why DMA transfert from DDR to internal does work on test 2 to 8 while it work on test 1 and while I don't get any issue with DMA transfert from internal RAM to DDR.
Hi Sebastien, it seems like there is some slight bug in the EDMA code which is not allowing the DMA to complete. Can you check the EMR register (address 0x49000300) to see if any events were missed? Missed events can occur if the previous event did not complete or did not get serviced.
If you run the EDMA tests individually, do they pass? If so, then i think the problem lies somewhere in the successive DMAs that are being setup in the test.
At any rate, it seems like the DDR configuration you have now is working, correct? Now it just seems to be a DMA issue?
Concerning "PHY ready" Issue, I think it is solve. I've kept my sdcard connected at power so I suspect config issue when GEL overwrites the EMIF config.
Concerning EDMA test failure:
I've displayed the EMR content. It is always 0x0I also check the IPR content before starting DMA, after it ends, and after it is cleared.IPR value is as expected: 0 before starting DMA 1 when it ends 0 after clearingSo it means DMA transfer is executed but memory content is not updated.So I checked at 0x4900 4004, at 0x4900 4008, and at 0x4900 400C the src, size and dst address registers. They are correct.As written before, if I don't use the same src address for test 1 as for test 2 for DMA transfer from DDR to internal Ram. That case works well.for example (original GEL) Test 1 DDR (0x8000 0000) > Int Ram (0x4030 0000) > PASS Int Ram (0x4030 0800) > DDR (0x8000 0800) > PASS Test 2 DDR (0x8000 0000) > Int Ram (0x4030 0000) > FAIL Int Ram (0x4030 0800) > DDR (0x8000 0800) > PASSfor example (updated GEL to pass) Test 1 DDR (0x8000 0000) > Int Ram (0x4030 0000) > PASS Int Ram (0x4030 0800) > DDR (0x8000 0800) > PASS Test 2 DDR (0x8000 0000) > Int Ram (0x4030 1000) > PASS Int Ram (0x4030 1800) > DDR (0x8000 0800) > PASS
what's your point of view about it?
Sebastien, I'm still not sure why you are having trouble with the DMA. What you are doing should be possible.
Can you check to see if you are having some addressing issue by doing the following: Write a unique value to each location of DDR (for example, write 0x80000000 to address 0x80000000, write 0x80000004 to address 0x80000004, etc). You should be able to write a quick GEL script for this. This will check to make sure you don't have any addressing issues or aliasing going on.
I tried your same test case GEL functions on my EVM, and it passed. So you may want to expand the test to different addresses to maybe see a pattern.
I did the test you ask me but it is a long too long test (256MB ram size). So I used the Row / Col addressing mode of the memory to reduce the test time by 1024 (because my memory as 10 bit col address).
So my test loop test only the 14+3 bits (Row addess + bank) shifting the incremented valeur by 10 bits according to the REG_IBANK_POS value and the REG_EBANK_POS value
The result is pass.
May it possible to share the GEL file you use on you EVM? Here I don't have other board having a JTAG connector. So I cannot try with other plateform?
Sebastien, here is the GEL i used.
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