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TMS320C6657: Multicore Navigator

Prodigy 170 points

Replies: 2

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Part Number: TMS320C6657

Hi,

We are using the C6657 (two C66x Cores).
In our application we have to maintain a core to core async communication.
The messages rate from core 1 to core 0 should be around 1000 Messages per second,
and the length of each message is about 1KB (max length).
The messages rate from core 0 to core 1 should be around 100-200 Messages per second.
and the length of each message is about 64 Bytes (max length).

I've looked on the Multicore Navigator (QMSS, PHTDMA and MessageQ), what is
the preffered way for our case?

Is there a code example for such transfers which send messages between the two cores?

Thank you

  • Hi,

    Let me take a look at this and I will update.

    Best Regards,
    Yordan

     


     Please make sure you read the forum guidelines first.

  • In reply to Yordan Kovachev:

    Hi Eyal,

    You may refer to the IPC messageq test code shown in the ipc_3_50_03_05\examples\C6678_bios_elf\ex11_ping\. IPC package is available from Processor SDK - 

    You need specify the MultiProc.numProcessors = 2 in .cfg file to port the C6678 example to C6657.


    >>The messages rate from core 1 to core 0 should be around 1000 Messages per second,
    >>and the length of each message is about 1KB (max length).

    With the high data rate (1MB/s, i.e. 1us per byte), you may need a mechanism as in the big data example which transfers the shared data buffer descriptor (address pointers) only - http://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/index_examples_demos.html?highlight=big%20data#big-data-ipc-example Note the big data example is available for AM57x only.

    Regards,

    Garrett