Hi,
I modified the PCIe example project to set it up in PHY loopback mode. I followed the steps listed in the user manual and it looks like everything is working but I'm seeing some strange behavior.
After I send the data from RC, I query the fatal, non-fatal, correctable, unsupported request error bits in the DEV_STAT_CTRL register. The unsupported request error bit is always coming back as a 1, along with the non-fatal error bit. But, the destination buffer matches the source buffer and I see "Root complex received data" message in the console.
Any thoughts on why those bits are being set to 1 and yet the loop back mode succeeds?
Thanks,
Viney