Hi,
Just a quick confirmation about input clock requirement in internal DDR3 PLL sysbsystem.
Here is a snippet from C6678 datasheet. The requirement for DDR3 clock pins is 40Mhz(min), but because of PLLD, the clock can be smaller than 40Mhz just before PLLM input stage. I could not see any related restrictions in datasheet, so believe it should be ok, but please let me confirm just in case. Also, I would like to know the clock speed requirements/usage note about the inside of other PLL sysbsystems (Like main PLL, PA PLL, and etc..) if you have.
Best Regards,
Naoki
