Hello, we are trying to use the K2L EVM board (document ## 16_00176_03, Rev 3.03, June 15 2017) with a JESD interface. The schematics show on sheet 10 of 47 the connector pin out for the FMC1 with signals JESD1_TXP_FMC1 AND JEST1_TXN_FMC1 on pins A22 and A23. It also shows the JESD2_TXP_FMC1 AND JESD2_TXN_FMC1 on pins A26 and A27. The schematics has a big red circle around these pairs. Is this because these pairs are called out incorrectly in the table inserted in the schematic on sheet 12 of 47? Our interface board is utilizing the JESD ports according to the schematic:
lamar process balls AG19/AG18 (schematic signal names JESD1/AIF0_TXP_SOC, JESD1/AIF0_TXN_SOC) drive the JESD switch (U32) at pins 15/16 (schematic signal names JESD1_TXP_FMC1, JESD1_TXN_FMC1) which are then ac coupled to the FMC1 connector pins A22/A23.
is this correct?
Also, since the JESD switch is used, what do I need to do to set up the Xilinx which generates the multiplexing control on the switch accommodate my JESD lane arrangement on our board with both a DAC and ADC:
Our hardware JESD lane setup for our protoboard connected to the EVM:
For our DAC: (Using JESD subclass1, with 122.88MHZ CLOCK with 120KHZ sys ref as generated from EVM)
66AK2L06 transmit output [SHARED_SERDES_0] JESD channel 0 differential pins AH18/AH17 => ROUTE TO => FMC1 connector differential pins C2/C3
66AK2L06 transmit output [SHARED_SERDES_0] JESD channel 1 differential pins AG19/AG18 => ROUTE TO => FMC1 connector differential pins A22/A23
For our ADC: (Using JESD subclass 1, with 122.88MHZ CLOCK with 120KHZ sys ref as generated from EVM)
66AK2L06 receive input [SHARED_SERDES_0] JESD channel 0 differential pins AJ18/AJ19 <= ROUTE FROM <= FMC1 connector differential pins C6/C7
66AK2L06 receive input [SHARED_SERDES_0] JESD channel 1 differential pins AK19/AK20 <= ROUTE FROM <= FMC1 connector differential pins A2/A3