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TCI6638K2K: TCI6638K2K

Part Number: TCI6638K2K

Hi Team,

For TCI6638K2K SOC- CVDD smart reflex supply - (0.8V to 1.1V) LM10011 and TPS544C25 device is used.
TPS544C25 part supports 30A max.

Say K2K estimator sheet worst case power is calculated to be 23W. In this case, if voltage is 1V then current is 23A but if it is 0.8V, current can increase till 29A. Will this 30A device still support in this case? what is the derating % of the IC?

Or should we look for another converter 35A/40A part for TPS544C25 (30A) part?

Also I referred to sprabv0 - page 10 smart reflex VID value mapping - How is this mapping done?
Is this controlled by TI SOC? There is no hardware setting for this part. VCNTL control between TI SOC and LM10011 DAC does this mapping.

Please revert asap.

Thanks and Regards,

Vidhya

  • Hi,

    If you're sure that the worst case scenario has a consumption of 29A, then the 30A device should do.
    However, if you wish to be absolutely sure (have a reserve) go with the 35/40 A devices.

    The VID code is connected to VCNTL pins of the keystone devices. See Section 2.2.1 CVDD from the Hardware design guide for more information:
    www.ti.com/.../sprabv0.pdf

    Best Regards,
    Yordan
  • Vidhya,

    The VID code is generated from within the 66AK2H14.  The LM10011 translated this into a current relative to the VID code setting.  This in trun can be used to control the output from a power conversion device like the TPS544C25.  The UCD9244 is a digital power controller and it is programmed to directly accept the VID code and generate the desired voltage.

    Tom

  • Thanks Yordan and Tom.

    I have one query on the load transient.

    What would be the load transient step for TPS544C25 (30A max) part? Is there any thumb rule for the same? What is the slew rate( A/us)?

    Regards,

    Vidhya

  • Vidhya,

    You have indicated that you used the power estimation spreadsheet for your application.  Once you put in the use case information and configure it for the maximum operating temperature, it displays the maximum power (or current) consumption per voltage rail.  It also displays separately the 'baseline' current and the 'activity' current .  The worst-case load step size can be bounded by this activity current value.

    The DSPs can transition from idle to full processing very quickly.  This can result in very fast slew rates for the load step.  I recommend that you design your power supply loop filter for at least 0.5A/us.  I believe the digital control loop for the CVDD supply was implemented with a slew rate of 1.0A/us.

    Tom

  • Hello Tom,

    1. The estimator sheet has options for power and current visibility. But the power to current conversion for the smart reflex CVDD of the TI SOC is done for 0.9V by default. TI SOC TCI6638K2K supports 0.8V to 1.1V. What is the reason for setting up the estimator for 0.9V CVDD rail while SOC can support even lesser voltage?

    2. So based on baseline and Dynamic changes Load transient current is identified to be 16A worst case. but how to identify the duration of this transition (in micro seconds / milli seconds?).

    3. I observed Itran=10A mentioned in TPS544C25 datasheet. Does it imply 20A of static current and 10A of dynamic current the device (30A part ) supports? Correct me if not.

    3. Slew rate setting is in V/us through VOUT_TRANSITION_RATE Command. It is then more related to settling time for voltage rather than slew rate?  

    4. LC loop filter design is done with expected load current change. How is the loop filter and slew rate related? is it based on capacitor discharge/Charge time RC time constant? Please clarify.

    Regards,

    Vidhya

  • Tom,

    As you have mentioned, the VID code is generated from within the 66AK2H14. In our case it is 6638K2K. so VID code generation is not under hardware control , there are no separate register VID Code settings at SOC hence no Software control? on what basis this VID code is generated?
    Please Clarify.

    Regards,
    Vidhya
  • Vidhya,

    1. The estimator sheet has options for power and current visibility. But the power to current conversion for the smart reflex CVDD of the TI SOC is done for 0.9V by default. TI SOC TCI6638K2K supports 0.8V to 1.1V. What is the reason for setting up the estimator for 0.9V CVDD rail while SOC can support even lesser voltage?

    TI: 0.9V is about the lowest AVS voltage seen in actual operation for these high performance devices. The silicon process will operate at lower voltages but not at these clock frequencies. Therefore using the 0.9V conversion is sufficient to properly size your power supply components.

    2. So based on baseline and Dynamic changes Load transient current is identified to be 16A worst case. but how to identify the duration of this transition (in micro seconds / milli seconds?).

    TI: How are you getting 16A of activity current? Setting all of the processing units to 100% is not reality. Software routines cannot be written the use all execution units at 100% sustained. Also, accesses to memories outside the cores also reduce execution levels. For instance control code written in ‘C’ will only load the C66 DSP cores at about 11% (even though you are using an optimizing compiler). Signal processing code hand-written in assembly will only load the C66 DSP cores at about 27%. For realistic applications with this processor, your maximum active power will be less than 8A and probably less than 5A.

    TI: As answered previously, you should assume 1A/us for selecting your power stage components and the control loop parameters. The power stage of the supply cannot realistically respond faster than this. The higher frequency current demand must be met from the ceramic decoupling caps distributed around the CVDD plane.

    3a. I observed Itran=10A mentioned in TPS544C25 datasheet. Does it imply 20A of static current and 10A of dynamic current the device (30A part ) supports? Correct me if not.

    TI: This reference in the datasheet for the TPS544C25 device is simply an example. There is no assumption for the baseline current in this calculation. It is simply focused on transient analysis with a 10A load step.

    3b. Slew rate setting is in V/us through VOUT_TRANSITION_RATE Command. It is then more related to settling time for voltage rather than slew rate?

    TI: The VOUT_TRANSITION_RATE is a slew rate limit for output voltage transitions when commanded over the PMBUS. This is in units of mV/uS. This is very slow relative to the power supply control loop.

    4. LC loop filter design is done with expected load current change. How is the loop filter and slew rate related? is it based on capacitor discharge/Charge time RC time constant? Please clarify.

    TI: This is explained in the datasheet for the chosen power supply in the Application section. Please request support from the power teams for support with this process.

    5. As you have mentioned, the VID code is generated from within the 66AK2H14. In our case it is 6638K2K. so VID code generation is not under hardware control , there are no separate register VID Code settings at SOC hence no Software control? on what basis this VID code is generated?

    TI: This device uses Smart Reflex Class 0 (SRc0). There are many discussions on E2E about this technology. The silicon process used to manufacture chips such as the TCI6638K2K varies from chip to chip. The distribution is Gaussian so there is an average process strength per wafer or per the entire population of devices produced. Devices with higher process strength run faster but have higher leakage current. Devices with lower process strength have lower leakage but run slower. Similarly, increasing the core supply voltage causes the silicon to run faster but this also increases active and leakage currents. Smart Reflex Class 0 is a process used to speed up devices with lower process strength by running them at higher voltages and reduce current consumption in devices with higher process strength by running them at lower voltages. Since the process strength of a device does not change over time, an algorithm is used during production test to establish the process strength and to then program into the device a VID code that translates to a required CVDD voltage. After this value is determined, the device is operated at this voltage while verifying that it operates at the rated speed and also that it operates under the maximum current threshold. This same VID code is used on the customer board to provide the proper voltage to the device by the SRc0 compliant power supply. These VID codes vary from device to device.

    Tom

  • Thanks Tom.

    Please find my response in line.

    1. Ok. 0.9V voltage consumes lesser current compared to 0.8V for same wattage.

    2. 16A is considered based on 75% utilization for other peripherals, 50% for SP and 50% for CC utilization. 

    3. As you have mentioned, 1A/us will be a realistic number. But to check the load transient by pulling extra load using external electronic load from 75% to 100% current can't be vaildated with 1A/us.what would be the realistic slew rate to achieve this? 

    3a. ok

    3b. But this Vout transition rate is an impact of the power supply control loop right? How less is my mV/us will define a better loop response. Correct me if not.

    4. Ok.

    5. So you mean if at production test, Higher ( Low core voltage) /Lower  (Higher core voltage) process strength is identified for the silicon to best operate, then output voltage is fixed?

    Say TCI6638K2K is identified to best operate at 1V core voltage at production manufacturing test, 1V is the fixed core supply?

    Kindly revert.

    Regards,

    Vidhya

  • Vidhya,

    Responses spliced in below:

    1. The estimator sheet has options for power and current visibility. But the power to current conversion for the smart reflex CVDD of the TI SOC is done for 0.9V by default. TI SOC TCI6638K2K supports 0.8V to 1.1V. What is the reason for setting up the estimator for 0.9V CVDD rail while SOC can support even lesser voltage?

    TI: 0.9V is about the lowest AVS voltage seen in actual operation for these high performance devices.  The silicon process will operate at lower voltages but not at these clock frequencies.  Therefore using the 0.9V conversion is sufficient to properly size your power supply components.

    Vidhya:  Ok. 0.9V voltage consumes lesser current compared to 0.8V for same wattage.

    2. So based on baseline and Dynamic changes Load transient current is identified to be 16A worst case. but how to identify the duration of this transition (in micro seconds / milli seconds?).

    TI: How are you getting 16A of activity current?  Setting all of the processing units to 100% is not reality.  Software routines cannot be written the use all execution units at 100% sustained.  Also, accesses to memories outside the cores also reduce execution levels.  For instance control code written in ‘C’ will only load the C66 DSP cores at about 11% (even though you are using an optimizing compiler).  Signal processing code hand-written in assembly will only load the C66 DSP cores at about 27%.  For realistic applications with this processor, your maximum active power will be less than 8A and probably less than 5A.

    Vidhya:  16A is considered based on 75% utilization for other peripherals, 50% for SP and 50% for CC utilization.

    TI: Like I said previously, actual utilization will not yield a part that consumes that much current. Even hand assembled and optimized DSP routines will not get close to 50% SP plus 50% CC. Keep in mind the C66x DSP has 8 execution units per core. Hand assembled and optimized DSP routines that have data and program fully cached in local memory can only obtain about 2.5 executions per clock cycle. This is only obtained for cached program and local data. All accesses outside the reduce this level. You should set the levels at 27% SP and 11% CC for realistic estimated of the maximum current draw. Similarly, most peripherals will not be loaded anywhere close to 75%. Even DDR which may be the most heavily used peripheral usually peaks at less than 50% reads and 15% writes. Other peripherals, if used after booting, are normally in the 10-20% range.

    TI: As answered previously, you should assume 1A/us for selecting your power stage components and the control loop parameters. The power stage of the supply cannot realistically respond faster than this. The higher frequency current demand must be met from the ceramic decoupling caps distributed around the CVDD plane.

    Vidhya: As you have mentioned, 1A/us will be a realistic number. But to check the load transient by pulling extra load using external electronic load from 75% to 100% current can't be validated with 1A/us. What would be the realistic slew rate to achieve this?

    TI: I do not understand this response. There are electronic loads that can be programmed for 1A/uS and they can be programmed for stepping from 75% to 100% of the programmed load current. If the equipment that you have has a maximum slew rate that is slower, then you should set it to the fastest that it can operate.

    3a. I observed Itran=10A mentioned in TPS544C25 datasheet. Does it imply 20A of static current and 10A of dynamic current the device (30A part ) supports? Correct me if not.

    TI: This reference in the datasheet for the TPS544C25 device is simply an example. There is no assumption for the baseline current in this calculation. It is simply focused on transient analysis with a 10A load step. 

    Vidhya: ok

    3b. Slew rate setting is in V/us through VOUT_TRANSITION_RATE Command. It is then more related to settling time for voltage rather than slew rate?

    TI: The VOUT_TRANSITION_RATE is a slew rate limit for output voltage transitions when commanded over the PMBUS. This is in units of mV/uS. This is very slow relative to the power supply control loop.

    Vidhya: But this Vout transition rate is an impact of the power supply control loop right? How less is my mV/us will define a better loop response. Correct me if not.

    TI: No, the VOUT_TRANSITION_RATE must be much slower (10x to 100x slower) than the control loop so that it does not affect stability.

    4. LC loop filter design is done with expected load current change. How is the loop filter and slew rate related? is it based on capacitor discharge/Charge time RC time constant? Please clarify.

    This is explained in the datasheet for the chosen power supply in the Application section. Please request support from the power teams for support with this process.

    Vidhya: Ok.

    5. As you have mentioned, the VID code is generated from within the 66AK2H14. In our case it is 6638K2K. so VID code generation is not under hardware control , there are no separate register VID Code settings at SOC hence no Software control? on what basis this VID code is generated?

    TI: This device uses Smart Reflex Class 0 (SRc0). There are many discussions on E2E about this technology. The silicon process used to manufacture chips such as the TCI6638K2K varies from chip to chip. The distribution is Gaussian so there is an average process strength per wafer or per the entire population of devices produced. Devices with higher process strength run faster but have higher leakage current. Devices with lower process strength have lower leakage but run slower. Similarly, increasing the core supply voltage causes the silicon to run faster but this also increases active and leakage currents. Smart Reflex Class 0 is a process used to speed up devices with lower process strength by running them at higher voltages and reduce current consumption in devices with higher process strength by running them at lower voltages. Since the process strength of a device does not change over time, an algorithm is used during production test to establish the process strength and to then program into the device a VID code that translates to a required CVDD voltage. After this value is determined, the device is operated at this voltage while verifying that it operates at the rated speed and also that it operates under the maximum current threshold. This same VID code is used on the customer board to provide the proper voltage to the device by the SRc0 compliant power supply. These VID codes vary from device to device.

    Vidhya: So you mean if at production test, Higher ( Low core voltage) /Lower  (Higher core voltage) process strength is identified for the silicon to best operate, then output voltage is fixed?

    TI: Yes, a unique value for that specific device is programmed as its VCNTL value. This value is output on the VCNTL lines during operation to control the voltage generated by the SRc0 compatible power supply.

    Tom

  • Thanks Tom. 

    My responses in line.

    1. The estimator sheet has options for power and current visibility. But the power to current conversion for the smart reflex CVDD of the TI SOC is done for 0.9V by default. TI SOC TCI6638K2K supports 0.8V to 1.1V. What is the reason for setting up the estimator for 0.9V CVDD rail while SOC can support even lesser voltage?

    TI: 0.9V is about the lowest AVS voltage seen in actual operation for these high performance devices.  The silicon process will operate at lower voltages but not at these clock frequencies.  Therefore using the 0.9V conversion is sufficient to properly size your power supply components.

    Vidhya:  Ok. 0.9V voltage consumes lesser current compared to 0.8V for same wattage.

    2. So based on baseline and Dynamic changes Load transient current is identified to be 16A worst case. but how to identify the duration of this transition (in micro seconds / milli seconds?).

    TI: How are you getting 16A of activity current?  Setting all of the processing units to 100% is not reality.  Software routines cannot be written the use all execution units at 100% sustained.  Also, accesses to memories outside the cores also reduce execution levels.  For instance control code written in ‘C’ will only load the C66 DSP cores at about 11% (even though you are using an optimizing compiler).  Signal processing code hand-written in assembly will only load the C66 DSP cores at about 27%.  For realistic applications with this processor, your maximum active power will be less than 8A and probably less than 5A.

    Vidhya:  16A is considered based on 75% utilization for other peripherals, 50% for SP and 50% for CC utilization.

    TI: Like I said previously, actual utilization will not yield a part that consumes that much current. Even hand assembled and optimized DSP routines will not get close to 50% SP plus 50% CC. Keep in mind the C66x DSP has 8 execution units per core. Hand assembled and optimized DSP routines that have data and program fully cached in local memory can only obtain about 2.5 executions per clock cycle. This is only obtained for cached program and local data. All accesses outside the reduce this level. You should set the levels at 27% SP and 11% CC for realistic estimated of the maximum current draw. Similarly, most peripherals will not be loaded anywhere close to 75%. Even DDR which may be the most heavily used peripheral usually peaks at less than 50% reads and 15% writes. Other peripherals, if used after booting, are normally in the 10-20% range.

    -Yeah makes sense. 

    TI: As answered previously, you should assume 1A/us for selecting your power stage components and the control loop parameters. The power stage of the supply cannot realistically respond faster than this. The higher frequency current demand must be met from the ceramic decoupling caps distributed around the CVDD plane.

    Vidhya: As you have mentioned, 1A/us will be a realistic number. But to check the load transient by pulling extra load using external electronic load from 75% to 100% current can't be validated with 1A/us. What would be the realistic slew rate to achieve this?

    TI: I do not understand this response. There are electronic loads that can be programmed for 1A/uS and they can be programmed for stepping from 75% to 100% of the programmed load current. If the equipment that you have has a maximum slew rate that is slower, then you should set it to the fastest that it can operate.

    -Ok .I will check this out.

    3a. I observed Itran=10A mentioned in TPS544C25 datasheet. Does it imply 20A of static current and 10A of dynamic current the device (30A part ) supports? Correct me if not.

    TI: This reference in the datasheet for the TPS544C25 device is simply an example. There is no assumption for the baseline current in this calculation. It is simply focused on transient analysis with a 10A load step. 

    Vidhya: ok

    3b. Slew rate setting is in V/us through VOUT_TRANSITION_RATE Command. It is then more related to settling time for voltage rather than slew rate?

    TI: The VOUT_TRANSITION_RATE is a slew rate limit for output voltage transitions when commanded over the PMBUS. This is in units of mV/uS. This is very slow relative to the power supply control loop.

    Vidhya: But this Vout transition rate is an impact of the power supply control loop right? How less is my mV/us will define a better loop response. Correct me if not.

    TI: No, the VOUT_TRANSITION_RATE must be much slower (10x to 100x slower) than the control loop so that it does not affect stability.

    -ok. 

    4. LC loop filter design is done with expected load current change. How is the loop filter and slew rate related? is it based on capacitor discharge/Charge time RC time constant? Please clarify.

    This is explained in the datasheet for the chosen power supply in the Application section. Please request support from the power teams for support with this process.

    Vidhya: Ok.

    5. As you have mentioned, the VID code is generated from within the 66AK2H14. In our case it is 6638K2K. so VID code generation is not under hardware control , there are no separate register VID Code settings at SOC hence no Software control? on what basis this VID code is generated?

    TI: This device uses Smart Reflex Class 0 (SRc0). There are many discussions on E2E about this technology. The silicon process used to manufacture chips such as the TCI6638K2K varies from chip to chip. The distribution is Gaussian so there is an average process strength per wafer or per the entire population of devices produced. Devices with higher process strength run faster but have higher leakage current. Devices with lower process strength have lower leakage but run slower. Similarly, increasing the core supply voltage causes the silicon to run faster but this also increases active and leakage currents. Smart Reflex Class 0 is a process used to speed up devices with lower process strength by running them at higher voltages and reduce current consumption in devices with higher process strength by running them at lower voltages. Since the process strength of a device does not change over time, an algorithm is used during production test to establish the process strength and to then program into the device a VID code that translates to a required CVDD voltage. After this value is determined, the device is operated at this voltage while verifying that it operates at the rated speed and also that it operates under the maximum current threshold. This same VID code is used on the customer board to provide the proper voltage to the device by the SRc0 compliant power supply. These VID codes vary from device to device.

    Vidhya: So you mean if at production test, Higher ( Low core voltage) /Lower  (Higher core voltage) process strength is identified for the silicon to best operate, then output voltage is fixed?

    TI: Yes, a unique value for that specific device is programmed as its VCNTL value. This value is output on the VCNTL lines during operation to control the voltage generated by the SRc0 compatible power supply.

    -Ok

  • Hi Tom,

    One query from K2E and K2L reference design on the TPS544C25.

    Why is there a schottky diode added at the output side?

    Kindly revert.

    Thanks,

    Vidhya

  • Vidhya,

    We implemented the power supply as directed by the development team.  We were developing the K2E EVM at the same time as the TPS544C25 was being developed.  This may have been needed for early prototypes.  I do not see it as a requirement in the TPS544C25 design collateral.  Therefore, it should not be needed in your design.

    Tom

  • Hi Tom,

       I see the usage of this schottky diode is to improve the efficiency by reducing the dead time between the switching from high side mosfet to low side mosfet.Though TPS544C25 is a synchronous Integrated MOSFET Buck converter, the load transient of the load-TI SOC response is slower, This schottky diode adds up in parallel to the body diode of low side FET and thereby with its less recovery time characteristics it improves the efficiency.

    I am not sure how practically this diode would have helped.

    How should we go about this? Do you recommend to use it or remove it from our design?

    Regards,

    Vidhya

  • Vidhya,

    My recommendation is to implement this diode unless you get approval from the power supply applications experts that it is not required.

    Tom

  • Thanks Tom.

    I have queries on the TPS51200 part. 

    1. This part can source up to 4.5A max and sink up to 5.5A max (mentioned in datasheet spec). But in TI site it is mentioned as


    3A Sink/Source DDR Termination Regulator w/ VTTREF Buffered Reference for DDR2, DDR3, DDR3L and DDR4

     can you please confirm if it can support 4.5A and 5.5A max?

    2. our requirement is to power 10*DDR3 ICs. so there are 14 address lines,6command lines and 3 control lines=28 lines in total. 12mA for sourcing and 13mA for sinking.

    for one IC, VTT current =28*13= 0.35A 

    For 10 IC, Current is 3.5A. 

    will TPS51200 support this need?

    Kindly confirm at the earliest.

    Appreciate your help.

    Thanks and Regards,

    Vidhya

  • Vidhya,

    You keep adding on different questions to the same E2E thread.  Please open a new one and I will answer the TSP51200 quesitions there.

    Tom