Other Parts Discussed in Thread: SYSBIOS
Tool/software: TI-RTOS
We have the following configuration:
K2H12 processor with DDR3 SDRAM
Main application running on ARM-0 under TI-RTOS
Support functions running on 2 DSP cores
Processors use IPC to pass data
A small amount of control data is passed in MSMC.
The ARM software writes to MSMC, flushes cache, and signals the target processor. The target processor invalidates memory before reading. The DSPs also pass data back to the ARM: they define MSMC as non-cached. They write to MSMC and then signal. The ARM invalidates the cache area before reading results.
The DSPs turn disable caching for the MSMC space using:
CACHE_invAllL1dWait();
CACHE_invL2Wait();
CACHE_disableCaching (MSMC_ADDRESS >> 24);
Where MSMC_ADDRESS is 0x0c000000.
Observations:
- From the debugger, on the DSP, we can see the writes to MSMC. They are consistent between the local memory and physical memory views; cache appears to be disabled on the DSPs as desired.
- When running ARM code compiled as target configuration = debug, both local memory and physical memory show the values written by the DSP, whether we invalidate or not.
- When running the same ARM application compiled as target configuration as release, the debug pod with the ARM0 target shows that the local and physical memory contents, but neither agrees with what the DSP wrote. (All processors were stopped and we stepped through the DSP code to perform the writes, and stepped through the ARM code to confirm invalidates). Also, the ARM's view of memory is no different before the cache invalidate than after. The invalidate call on the ARM is:
Cache_inv (addr, sizeof(data area), Cache_Type_ALLD, TRUE).
The data area is within MSMC, and agrees with the address used by the DSPs. It is 12 floats long, and is aligned to a 256 byte boundary. We have confirmed addresses and lengths by stepping into the invalidate routines and examining register values; they are correct.
1) Is this a correct procedure for passing data between the DSPs and ARM cores? Are there better alternatives?
2) We would like the ARM to treat MSMC as non-cached. With no caching on either processor, our understanding is that we may have to do something to flush the pipelines during stores, and that the data passing should work. However, we are not sure how to declare that MSMC is non-cacheable from the ARM's perspective. We appear to have achieved this from the DSP side. How does one configure MSMC address space as non-cachable from within the ARM?
Thanks and regards,
Tim
