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DRA71: The output impedance settings of HDMI output pins

Part Number: DRA71

Hi

    In dra71x datasheet<DRA71x Infotainment Applications Processor>,there is description about the  impedance settings of the hdmi out pins  in Page 64. table 4-1

(8) In PUx / PDy, x and y = 60 to 200 μA.
The output impedance settings (or drive strengths) of this IO are programmable (34 Ω, 40 Ω, 48 Ω, 60 Ω, 80 Ω) depending on the values of the I[2:0] registers.

 

But i could not find which register to configure this ,pls help check about it .

Thanks,

 

  • Hi,

    Note (8) doesn't correspond to HDMI, although you are right to think so because of the Pdy marking.

    As you already noticed, there is no pullup/down registers for HDMI data and clock lanes. Instead, they are located (if any)  in the HDMI PHY register space.

    I've checked the HDMI PHY document and even didn't see a functuon of programmable pulldowns or pullups. The only similar function appears to be the external pullup detection circuit:

    "The HDMI_PHY can detect a pullup to 3.3V on any clock and data lines. This situation occurs when an

    external HDMI receiver is connected/disconnected to/from the device. The connection/disconnection leads

    to raising the RXDET error signal to the HDMI_WP module and generating interrupts to the device

    interrupt controllers (INTCs)."


    Looks like TRM register CTRL_CORE_CONTROL_HDMI_TX_PHY enables the pullup detection.

    Note that this detection is operating only during low power mode, when HDMI is not active. When HDMI is transmitting, pullup detection or internal pulls cannot be active.

    Regards,

    Stan