TMS320C6742: Problem with 32Mbit mDDR

Hello Everybody,
Recently I have ordered a small batch of PCBs with modified BOM to check for possible reduction of cost in mass production.
Original board has C6746 DSP + 128Mbit mDDR ISSI IS43LR16800G-6BLI and it works fine.
New version is populated with C6742 + 32Mbit mDDR ISSI IS43LR16200D-6BLI. Core voltage of DSP on the new version is reduced from 1.3 to 1.2V and the rest is identical to original version. Unfortunately all my efforts to make this memory accessible by DSP were not successful.
Mobile DDR chip on newer version while having lower capacity also has slightly different internal organization:
128Mbit chip: 4 banks, 4096 rows, 512 columns
32Mbit chip: 2 banks, 2048 rows, 512 columns
Because of the difference in number of banks, 32Mbit chip has only one BA pin and it affects how EMRS (Extended Mode Register Set) command is invoked. On 128Mbit chip the diagram in the datasheet says that to write EMR register bank selection pins must be set as: BA1=1 and BA0=0. And for 32Mbit chip it is needed to set BA0=1. It seems to me that it could be the cause of the problem. I suppose that DSP while initializing mDDR memory overwrites MR register with value intended for EMR register and does not initialize EMR at all.
This rises a question to Texas Instruments experts: could you please specify, how DSP determines needed logical combination on address and bank pins to access EMR register? Or is it a fixed pattern that only works on 128Mbit and larger chips?
More regarding my board and what I have tried to do. I connected new board with JTAG emulator and applied power. Power supply voltages are measured as 1.23V core & static and 1.81V DDR & IO. Voltages are applied with right sequence with 440uS delay. There is no observable voltage drops during mDDR initialisation or access. DSP clock is stable, it is provided externally from 24MHz crystal oscillator level-shifted to 1.2V with 74AUC1G17 gate. DSP itself work flawlessly while code and data lay in its internal memory.
Mobile DDR memory is initialized with a modified version of GEL file previously used with 128Mbit chip. I have corrected number of banks written to SDCR register but it did not work. Then I tried to enter actual number of rows in SDCR2 however it is required only for partial self-refresh mode that I don't use. Also tried reducing mDDR clock and timing parameters but nothing helped. I also experimented with bits affecting EMRS command to produce values that could be acceptable for MRS command too (suspecting command misinterpretation by mDDR chip). The best result I have got was to be able to enter 32-bit values by hand in memory editor, but they are written into neighbouring cell instead. For example, when I enter a number into cell with address 0xC0000000 it appears in the cell with address 0xC0000004 and the same is true in opposite direction. It looks to me like "misunderstanding" between DSP and mDDR in burst parameters. I tried two samples of new board and both work in the same way.

Thanks and regards
Mike