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66AK2G12: EVMK2GX has been bricked ?

Part Number: 66AK2G12
Other Parts Discussed in Thread: EVMK2GX, , 66AK2G02

Hi,

We sold some EVMK2GX (totally 3 boards, i think) to the customer but they could not access DDR3L correctly on one of them and it has been returned to my desk. Other EVMs we sold is working fine. I just run CCS with CCSv8 default gel file on the returned EVM and confirmed the following log on the console appeared. 

CortexA15: GEL Output: DDR3 PLL Setup ...
CortexA15: GEL Output: DDR3 PLL Setup complete, DDR3A clock now running at 533MHz.
CortexA15: GEL Output: DDR3A initialization complete

And then opened memory window and accessed the some region starting from 0x80000000, where it was for DDR3L data area. I should see the correct read/write operation on the region, but i saw very curious behavior. For example:

if i accessed to address of 0x80001000, i could see the following memory image.

And if i wrote 0xAAAAAAAA to 0x80001000, i got the following updated memory image.

It seems the write data had been shifted to other address....
I believe my test procedure itself should be correct and this EVM had been completely corrupted, or DDR configuration in gel file is not suitable for the existing DDR3 on the EVM.
Do you have any information about this phenomenon ?  Please note the board revision I`m now checking is D1.5. 

Best Regards,

NK

 

  • Kawada-san,

    Is the experiment from the board that is returned to be bricked or on all boards that you have. the GEL settings are used in board library and Linux and we have run DDR mem_tests and diagnsotics to validate the initialization so this is unlikely to be a GEL issue.

    I have looped in the board and DDR expert to comment on the phenomenon.

    Regards,
    Rahul
  • Hi Naoki,
    Do you have a 66AK2G02 or a 66AK2G12 installed on the EVM? Most of the EVMs were built with the K2G02 before the K2G12 was available. The K2G02 is only rated for DDR3 operation at 800MT/s with the DDR clock at 400MHz. You appear to be initializing the DDR at 1066MT/s.
    Regards, Bill
  • Hi Rahul-san, Bill-san

    Thank you for responding. I answer to your queries as below.

    Rahul said:
    Is the experiment from the board that is returned to be bricked or on all boards that you have. 

    We sold 3 EVMs to the customer, but one of them has been returned to my desk because of this phenomenon. The experiment I did is on a returned EVM.  As for other EVMs, I heard from the customer that they had confirmed to work with default gel.

    Bill Taboada said:
    Do you have a 66AK2G02 or a 66AK2G12 installed on the EVM?

    The returned EVM is EMVK2GX, so 66AK2G12 is mounted on the board.  If this is regarded as initial failure, we'll initiate replacement process to TIJ.

    Best Regards,
    NK

  • Hi Naoki-san,
    Would it be possible to attempt initializing the DDR3 at 800MT/s with a clock rate of 400MHz? I want to see if the DDR interface has some assembly issue that wasn't caught at the factory or if the board is not meeting the DDR speed target.
    Regards, Bill
  • Hello Bill,

    I did the experiment you suggested on the returned setup, but i still see the same problem.

    I modified the default gel file as below:

    Global_Default_Setup_Silent()
    {
    	int coreId = REG_CTXA15_CP15_C0_MPIDR & 0x3;
    	int devSpeed, armSpeed;
    
    	GEL_Reset();
    	
    	// Only core 0 can set these
    	if (coreId == 0)
    	{
    		GEL_TextOut( "Starting K2G GP EVM Initialization .. \n");
    		devSpeed = Read_device_speed (); 
    		armSpeed = Read_arm_speed ();
    		if (( devSpeed == 1000) && (armSpeed == 1000))
    		{
                /* This is 1000MHz chip */
    			CORE_PLL_INIT_24MHz_to_1000MHz();
    			TETRIS_PLL_INIT_24MHZ_to_1000MHz();
    			
            }
    		else if ((devSpeed == 600) && (armSpeed == 600))
    		{	
    			/* This is 600MHz chip */
    			CORE_PLL_INIT_24MHz_to_600MHz(); 
    			TETRIS_PLL_INIT_24MHZ_to_600MHz();
            }
    		else {
    			GEL_TextOut( "Device Variant not supported on the EVM .. \n");
    		}
    	    	
    		// Common configuration for 600 Mhz and 1Ghz variants
    		Set_Psc_All_On();
    		UART_PLL_INIT_24MHz_TO_384MHz();
    		NSS_PLL_INIT_24MHz_TO_1000MHz();
    		ICSS_POWERUP_AND_PLL_INIT_24MHz_to_200MHz();
    		DSS_PLL_INIT_24MHZ_to_25MHz();
    		InitXMC();
    /*
    		if (( devSpeed == 1000) && (armSpeed == 1000))
    		{
    			InitEmif_DDR3A_NO_ECC_1066MHz();
    		}
    		else{
    			InitEmif_DDR3A_NO_ECC_800MHz();
    		}
    */		
    		InitEmif_DDR3A_NO_ECC_800MHz();
            GEL_TextOut( "Forced 800MT/s for DDR3L \n");
    
            GEL_TextOut( "Entering A15 non secure mode .. \n");
            enterNonSecureMode();
            GEL_TextOut( "A15 non secure mode entered \n");
    		GEL_TextOut( "K2G GP EVM Initialization Complete. \n");
        }
    }
    
    

    As you see, I initialized DDR3A to work at 800Mhz.
    I confirmed the following log displayed when connecting the device in CCS:

    CortexA15: GEL Output: XMC setup complete.
    CortexA15: GEL Output: DDR3 PLL Setup ...
    CortexA15: GEL Output: DDR3 PLL Setup complete, DDR3A clock now running at 400MHz.
    CortexA15: GEL Output: DDR3A initialization complete
    CortexA15: GEL Output: Forced 800MT/s for DDR3L

    And then i did the same test. 

    Best Regards,
    NK

  • Hi Naoki,

    If it is not operating at 800MT/s than it sounds like a bad board. It should be returned so we can do an analysis to try and determine why it's failing and how it managed to pass the factory testing.

    Thanks, Bill

  • Hi Bill,

    Ok. So we will initiate the replacement process to TIJ. Do you agree ?

    Best Regards,
    NK

  • Hi Naoki,

    Since the DDR isn't operating at the lower speed, I agree that is should be returned.

    Regards,

    Bill