Other Parts Discussed in Thread: EVMK2GX, , 66AK2G02
Hi,
We sold some EVMK2GX (totally 3 boards, i think) to the customer but they could not access DDR3L correctly on one of them and it has been returned to my desk. Other EVMs we sold is working fine. I just run CCS with CCSv8 default gel file on the returned EVM and confirmed the following log on the console appeared.
CortexA15: GEL Output: DDR3 PLL Setup ...
CortexA15: GEL Output: DDR3 PLL Setup complete, DDR3A clock now running at 533MHz.
CortexA15: GEL Output: DDR3A initialization complete
And then opened memory window and accessed the some region starting from 0x80000000, where it was for DDR3L data area. I should see the correct read/write operation on the region, but i saw very curious behavior. For example:
if i accessed to address of 0x80001000, i could see the following memory image.
And if i wrote 0xAAAAAAAA to 0x80001000, i got the following updated memory image.
It seems the write data had been shifted to other address....
I believe my test procedure itself should be correct and this EVM had been completely corrupted, or DDR configuration in gel file is not suitable for the existing DDR3 on the EVM.
Do you have any information about this phenomenon ? Please note the board revision I`m now checking is D1.5.
Best Regards,
NK