Hello,
We are trying to implement the Errata SPRZ381C Advisory 3, DDR3 Automatic Leveling Issue, workaround 1. It mentions setting bit 9 (0 indexed) for the 4 byte lane registers and ECC. It also mentions that the lower 8 bits maybe be written or left as the default 0x34 value. In SPRUGV8e page 113 ( DDR3_CONFIG_52) it mentions that the reset value is 0xD034...
1. Is there a description explaining what the lower 20 bits are used for? Do I need to leave bits 15:12 = to 0xD? IE should I be writing value 0xD234 to enable the partial leveling?
Workaround 1 only mentions setting bit 9 and then if we want we can leave the lower 8 bits set to 0x34. Whereas SPRABL2e shows a bitwise oring of the value 0x200 with those registers... on page 14, section 3.2.1 example 21.
cheers,
