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AM5728: The display color of IDK-1110WR LVDS panel(18-bit) with AM-5728 Soc is NOT correct

Part Number: AM5728
Other Parts Discussed in Thread: DS90C187

1. Does AM-5728 Soc support the display color of 18-bit LVDS panel?

2. If it can support the display color of 18-bit LVDS panel, how do I modify the code?
I use "PROCESSOR-SDK-LINUX-AM57X 03_01_00_06" BSP to build code.
I previously asked TI's agent, they said we need to write the following values to the register on bootloader:
DISPC_CONFIG1 : Physical Address 0x5800 1044
 [15] CPR = 0x1: Color Phase Rotation Enabled
DISPC_CPR1_COEF_R : Physical Address 0x5800 1220
0x00800000
DISPC_CPR1_COEF_G : Physical Address 0x5800 1224
0x00001000
DISPC_CPR1_COEF_B : Physical Address 0x5800 1228
0x00000002

3. I have done two tests, but I still have problems.

a) Test Case 1:
I try to set suggestion values to the register on bootloader and boot the device, but the device still cannot work fine.
After I read these register values from kernel, I found that I set these values in the bootloader is different.

u-boot simple log:
=> mw 0x58001220 0x00800000
=> mw 0x58001224 0x00001000
=> mw 0x58001228 0x00000002
=> mw 0x58001044 0x0000820C
=> boot

Kernel simple log:
root@am57xxrom7510a2:~# devmem2 0x58001220
/dev/mem opened.
Memory mapped at address 0xb6f5b000.
Read at address 0x58001220 (0xb6f5b220): 0x00000000
root@am57xxrom7510a2:~#
root@am57xxrom7510a2:~# devmem2 0x58001224
/dev/mem opened.
Memory mapped at address 0xb6f7f000.
Read at address 0x58001224 (0xb6f7f224): 0x00000000
root@am57xxrom7510a2:~#
root@am57xxrom7510a2:~# devmem2 0x58001228
/dev/mem opened.
Memory mapped at address 0xb6f4f000.
Read at address 0x58001228 (0xb6f4f228): 0x00000000
root@am57xxrom7510a2:~# devmem2 0x58001044
/dev/mem opened.
Memory mapped at address 0xb6fd0000.
Read at address 0x58001044 (0xb6fd0044): 0x0000020C
root@am57xxrom7510a2:~#

b) Test Case 2:
I try to modify "dispc.c" file in kernel, but the device still cannot work fine.
After I read these register values from kernel, but it only first register value is changed.

b_1) Modify drivers/gpu/drm/omapdrm/dss/dispc.c:
static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
{
if (channel == OMAP_DSS_CHANNEL_DIGIT)
return;

mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);

#if 1
dispc_write_reg(0x220, 0x00800000);
dispc_write_reg(0x224, 0x00001000);
dispc_write_reg(0x228, 0x00000002);
dispc_write_reg(0x44, 0x820c);
#endif
}

b) Kernel simple log:
root@am57xxrom7510a2:~# devmem2 0x58001220
/dev/mem opened.
Memory mapped at address 0xb6fa9000.
Read at address 0x58001220 (0xb6fa9220): 0x00000000
root@am57xxrom7510a2:~#
root@am57xxrom7510a2:~# devmem2 0x58001224
/dev/mem opened.
Memory mapped at address 0xb6f66000.
Read at address 0x58001224 (0xb6f66224): 0x00000000
root@am57xxrom7510a2:~#
root@am57xxrom7510a2:~# devmem2 0x58001228
/dev/mem opened.
Memory mapped at address 0xb6f48000.
Read at address 0x58001228 (0xb6f48228): 0x00000000
root@am57xxrom7510a2:~# devmem2 0x58001044
/dev/mem opened.
Memory mapped at address 0xb6fdb000.
Read at address 0x58001044 (0xb6fdb044): 0x0000820C

Can you tell me how to solve this issue?

Thank you.

Best Regards,

Alex Cheng

  • HI Alex,

    The expert for this issue is out of the office at the moment. We should be able to get you some information by early next week. Sorry for the delay.
  • Hi Alex,

    Which bridge chip are you using to connect to LVDS panel on AM5728 device? I am assuming you are using linux OS. If so, can you please share the dts file settings for bridge chip and DSS? Also, please share the images of the incorrect display output that you are seeing.

    Regards,
    Manisha
  • Hi Manisha,

    We use "DS90C187" bridge chip to connect to LCD panel on AM5728 device. I use Linux Yocto 2.1 OS.

    The attached file is included the dts file settings for bridge chip/DSS and the images of the incorrect display output that I am seeing.

    FYI.

    You can search "dss" string to get "dss" information in am57xx-rom7510a2.dts file. You also can search "panel-timing" string to get the timing information of lcd panel in am57xx-rom7510a2.dts file.

    Thank you.

    Best Regards,

    Alex Cheng

    IDK-1110WR_LCD_display_data.zip

  • Hi Alex,

    Did you try changing the dss configuration for "data-lines = <24>;" to "data-lines = <18>;"? Accordingly, adjust the hardware connection between the DS90C187 with AM5728. to ignore the two msbs for each R, G and B lanes. 

    Regards,

    Manisha

  • Hi Manisha,

    I try to modify the dss configuration from "data-lines = <24>;" to "data-lines = <18>. But it still cannot work fine. Please see the incorrect image.

    Best Regards,

    Alex Cheng

  • Hi Alex,

    Did you adjust the hardware setting is removing the msb lanes when trying the data-line = <18>?

    Alternately, on your effort with using CPR, can you try the component value of 0x40, instead of 0x2.

    Note that, we support CPR from the userspace via the "ctm" (color transformation matrix) DRM property. You can use that to set the values from user space or hack the driver to set those values.

    Regards,
    Manisha
  • Hi Manisha,

    Do you mean using hardware rework to remove msb lanes? If 'yes', I have not tried hardware rework to remove msb lanes.
    Because we only consider whether it can be solved by software method about this problem.

    As I previously described in Test Case 2, I modified the values of four registers (0x58001220, 0x58001224, 0x58001228, 0x58001044) in the kernel source code.
    But after booting up, I read the values of the four registers, but only one register (0x58001044) has the same value as the code.
    Can you please tell me how to successfully modify the values of these four registers in the kernel source code?

    I don't know how to modify CPR via the "ctm" (color transformation matrix) DRM property.
    Can you tell me how to use it?

    Best Regards,

    Alex Cheng

  • Hi Alex,

    I hope you are using DRM APIs for DSS programming in user application. If yes, then you  can use drmModeAtomicAddProperty() API to set the DSS properties. To set CPR property, you need to use the property id as "ctm". To learn how to set DSS properties, you can check loopback.c file in dual-camera demo packaged in Processor SDK. Look for drm_init_dss() function. 

    Regards,

    Manisha

  • Hi Manisha,

    Unfortunately, I don't know how to use DRM APIs for DSS programming in the user application.

    Can you please provide me with the SOP for setting it up? I will set it up and verify it according to the method you provided.

    Thank you.

    Best Regards,

    Alex Cheng

  • Hi Alex,

    Please try removing the calls to dispc_mgr_enable_cpr and dispc_mgr_set_cpr_coef, to ensure that the registers are never set elsewhere.

    To hard code the settings inside the driver, please add the hard coded programming to _omap_dispc_initial_config().

    Regards,
    Manisha
  • Hi Manisha,

    I don't understand what you mean. Can you explain the following questions?

    Can you please describe in detail which function in the file is removed from the two functions((dispc_mgr_enable_cpr and dispc_mgr_set_cpr_coef)?

    What do you mean by "hard code" referring to the following four registers?

    dispc_write_reg(0x224, 0x00001000);
    dispc_write_reg(0x228, 0x00000002);
    dispc_write_reg(0x44, 0x820c);

    If not, what new hard code settings do I want to add?

    You say "please add the hard code programming to _omap_dispc_initial_config()", which function is in the file?

    Thank you.

    Best Regards,

    Alex Cheng

  • Hi Manisha,

    I don't understand what you mean. Can you explain the following questions?

    Can you please describe in detail which function in the file is removed from the two functions((dispc_mgr_enable_cpr and dispc_mgr_set_cpr_coef)?

    What do you mean by "hard code" referring to the following four registers?
    dispc_write_reg(0x220, 0x00800000);
    dispc_write_reg(0x224, 0x00001000);
    dispc_write_reg(0x228, 0x00000002);
    dispc_write_reg(0x44, 0x820c);

    If not, what new hard code settings do I want to add?

    You say "please add the hard code programming to _omap_dispc_initial_config()", which function is in the file?

    Thank you.

    Best Regards,
    Alex Cheng
  • Hi Manisha,

    I don't understand what you mean. Can you explain the following questions?

    Can you please describe in detail which function in the file is removed from the two functions((dispc_mgr_enable_cpr and dispc_mgr_set_cpr_coef)?

    What do you mean by "hard code" referring to the following four registers? If not, what new hard code settings do I want to add?
    dispc_write_reg(0x220, 0x00800000);
    dispc_write_reg(0x224, 0x00001000);
    dispc_write_reg(0x228, 0x00000002);
    dispc_write_reg(0x44, 0x820c);

    You say "please add the hard code programming to _omap_dispc_initial_config()", which function is in the file?

    Thank you.

    Best Regards,
    Alex Cheng
  • Hi Alex,

    Please find attached hack patch. Please try this -

    0001-HACK-hardcode-CRP-for-LCD.patch

    Regards,

    Manisha

  • Hi Manisha,

    Display still has problems. Please see the attached file.

    Thank you.

    Best Regards,

    Alex Cheng

  • Hi Alex,

    The register values provided in the patch were random, The patch was intended to get the register settings hard coded inside the driver code. It is up to the customers to set the right values for their need.

    I was updated by FAE that your issue was resolved after updating the register values. If so, please click "This resolved my issue" button and also update any other fixes that you needed to do to get the patch working. Thanks!

    Regards,
    Manisha
  • Hi Manisha,

    The issue was resolved. Thank you for your help.

    Best Regards,

    Alex Cheng