Tool/software: Code Composer Studio
Nand flash shares EMIF bus with FPGA. Will the use of DMA for reading and writing operation of NAND flash be affected by the interruption of FPGA?
Hi,
As Brad mentioned, there are up to four asynchronous chip selects, supported by EMIFA, these ate EMA_CS[2] to EMA_CS[5] and each of them has different individually programmable attributes such as NAND flash controller which supports ECC calculation. This is important to consider that the ECC calculation only could be done to that chip select space specified to the NAND flash. Take a look at the image below:
Assume that instead of the SDRAM there is an FPGA. Anyway, related to the image above, ECC calculation of NAND flash controller is done to chip select space specified to the NAND flash (EMA_CS[3] in this connection diagram).
We can conclude that the reading and writing operation of NAND flash could be NOT affected by the interruption of FPGA, due to the separate chip select spaces of NAND flash and FPGA, even when they share an EMIF bus with each other.
