RTOS/TMS320C6670: I would like to get help with multi-core project issues using PCIe.

Minjae Kim

Prodigy 100 points

Part Number: TMS320C6670

Tool/software: TI-RTOS

Hello

My goal is to send and receive data between Linux PC and DSP using PCIe.

More specifically.

It sends and receives data through PCIe between Linux PC and DSP Core0, The rest of the cores try to do the data operation.

also I want using SYS/BIOS.

This is my plan and the result.

using library:

C:\ti\mcsdk_2_01_02_06\tools\boot_loader\examples\pcie\linux_host_loader

=> Linux PC --- PCIe---> DSP

C:\ti\mcsdk_2_01_02_06\tools\boot_loader\examples\pcie\pcieboot_helloworld

=> Linux PC -> Core0 (Boot Code) -> Core 1

-> Core 2

-> Core 3

C:\ti\mcsdk_2_01_02_06\tools\boot_loader\examples\pcie\pcieboot_interrupt

=> Linux PC ---> PCIe ---> DSP (using EDMA Interrupt)

Linux PC <--- PCIe <--- DSP (using CSL Interrupt)

step

1. Combine Project pcie_boot_helloworld(Multi Core) and pcie_boot_interrupt( Interrupt)

For using multicore and interrupt

=> I've combined the two projects, but as a result, Only communication using Core0 PCIe was made and the rest of the cores did not work.

< pcie_boot_helloworld.cmd >

< pcie_boot_interrupt.cmd >

two project have difference memory section.

and HELLO_WORLD_DEMO in linux_host_loader using DDR(0x80000000)

EDMA_INTC_DEMO in linux_host loader using Cache(0x00800000)

I want to combine two project( helloworld and interrupt ) for using multicore and interrupt.

and

I want PCIe project combine SYS/BIOS.

please help me.

lding

I know you are a PCIe expert.

so I ask you for help.

thank you.

over 5 years ago

0 Minjae Kim over 5 years ago

Prodigy 100 points

help me lding

0 lding over 5 years ago in reply to Minjae Kim

TI__Guru* 95265 points

Hi,

There are several PCIE boot examples.

- The one for "hello world" is a two-step example, the host downloads an DDR INIT code first, letting it run to initialize DDR. Then the hello world is downloaded into DDR, this is a multiple core example, the core 0 is the master core and sends IPC interrupts to trigger other cores 1-7. The interrupt is between corepacs.

- The EDMA interrupt example is an EDMA + interrupt between host and DSP through PCIE interface.

I am not sure what you exactly do: it looks that you needs to use DDR for large data storage and processing, as L2 and MSMC may not big enough. And use DSP multiple cores in parallel processing and EDMA to speedup data movement, and interrupt to signal data is ready.

I would think,
1) you need download and run the DDR INIT application first to initialize the DDR.
2) Then you merge the examples "hello world" + EDMA interrupt above. The merged one needs to place common code in DDR, the local variables, stack, etc in local L2, as the hello world example.

The expectation is that you download this merged code into DDR, lets it run. Then host do an EDMA write (EDMA read from host memory into DSP) of bulk data into DSP data, then host sets an interrupt to DSP to tell it data is ready. This PCIE interrupt is only picked up by DSP core 0 ISR, you don't need other cores for this PCIE interrupt. From core 0, IPCGR is used to send interrupt to one cores where you have some algorithms for parallel processing.

When the data is processed, the core 0 do a EDMA write from DDR into host memory, then sends an interrupt via PCIE. Hope this explains the usage!

Regards, Eric

0 Minjae Kim over 5 years ago in reply to lding

Prodigy 100 points

Thank you for the reply.

so, I tried to merge that helloworld(based) + interrupt

In conclusion, It' does not work.

It's my Code

e2e_question.zip

It's my change point for merge

[ pcieboot_helloworld.c ]

Added CSL libraries for interrupts,

I added the define values and the interrupt setting part required for interrupts.

The start_boot () function in the "pcieboot_interrupt.c" was not added because it determined that "pcieboot_helloworld.c" overlapped with boot.