TMS320C5535: When is the USB DataEnd bit cleared?

J-breeze

Part Number: TMS320C5535

Hi Champs,

I'm referring to "Sequence #2" in the TRM(SPRUH87H) page.415 Figure 13-6.
The USB DataEnd bit is set when the Endpoint 0 is in the RX state in the sequence.

So, could you please let me know when the DataEnd bit is cleared?
I could not find the information in the TRM.

Regards,
J-breeze

over 5 years ago

0 Lalindra Jayatilleke over 5 years ago

TI__Mastermind 30365 points

J-breeze,

I believe the bit is cleared automatically.
Does the description on Table 13-89 bit 3 help?

Lali

0 J-breeze over 5 years ago in reply to Lalindra Jayatilleke

Expert 1105 points

Hi Lali,

I think the table you told me describe about setting the bit to 1, not clearing it to 0.
I'd like to make sure when the bit is cleared automatically.
Is it right after setting the bit? How long dose it take after setting the bit to 1?

Regards,
J-breeze

0 J-breeze over 5 years ago in reply to J-breeze

Expert 1105 points

Hi Lali,

Would you please give me some feedback?

Regards,
J-breeze

0 Lalindra Jayatilleke over 5 years ago in reply to J-breeze

TI__Mastermind 30365 points

J-breeze,

I'm checking on this internally.

Lali

0 J-breeze over 5 years ago in reply to Lalindra Jayatilleke

Expert 1105 points

Hi Lali,

Any update?

Regards,
J-breeze

0 Lalindra Jayatilleke over 5 years ago in reply to J-breeze

TI__Mastermind 30365 points

J-breeze,

No updates. Unfortunately, I don't know if we will be able to get a concrete reply for you since this is something very specific to the USB peripheral behavior not documented. I'm still trying to see if someone can provide a reply.

Is there a particular reason that this bit clearing time is essential for your application?

Lali

0 Ming Wei over 5 years ago in reply to Lalindra Jayatilleke

TI__Mastermind 41935 points

Hi J-breeze,

Here is the paragraph in the design document about the DataEnd:

The CPU sets this bit:

1. When setting TxPktRdy for the last data packet.

2. When clearing RxPktRdy after unloading the last data packet.

3. When setting TxPktRdy for a zero length data packet.

It is cleared automatically.

It is automatically cleared.

Ming

0 J-breeze over 5 years ago in reply to Ming Wei

Expert 1105 points

Hi Ming,

Thank you for your reply.
I really need the time spec. Would you have any data?

I have a problem with the following code in my application. The DataEnd bit is cleared and the EP0 state dose not move to the IDLE state from the RX state.

o app_usb.c
    (C:\ti\c55_lp\c55_caf_02.00.02.04\src)

    - Line 661~667

    /* check if data end bit is set */
      if((usbRegisters->PERI_CSR0_INDX & CSL_USB_PERI_CSR0_INDX_DATAEND_MASK) ==
      CSL_USB_PERI_CSR0_INDX_DATAEND_MASK)
          {
              pContext->ep0State = CSL_USB_EP0_IDLE;
          }
          /* else remain in rx state */

Regards,
J-breeze

0 J-breeze over 5 years ago in reply to J-breeze

Expert 1105 points

Hi Ming,

I'd like to ask again.
You told me that the DataEnd bit was automatically cleared. So, how long dose it take?

And I have one more question.
Is there a case that the bit does not change to 1 soon after the CPU sets this bit?

Best regards,
J-breeze

0 J-breeze over 5 years ago in reply to J-breeze

Expert 1105 points

Hi,

Any comment would be appreciated.

Best regards,
J-breeze

0 Ming Wei over 5 years ago in reply to J-breeze

TI__Mastermind 41935 points

Hi J-breeze,

Sorry for the delayed response. I was tied up with other high priority tasks.

If you exam the following code segment closely:

    if(CSL_USB_EP0_RX == pContext->ep0State)
    {
        if((usbRegisters->PERI_CSR0_INDX & CSL_USB_PERI_CSR0_INDX_RXPKTRDY_MASK) ==
         CSL_USB_PERI_CSR0_INDX_RXPKTRDY_MASK)
        {
            USB_readEP0Buf(pContext, pContext->wOutEP0Buf);
            pContext->fOutPhaseCmd = TRUE;

            /* check if data end bit is set */
            if((usbRegisters->PERI_CSR0_INDX & CSL_USB_PERI_CSR0_INDX_DATAEND_MASK) ==
            CSL_USB_PERI_CSR0_INDX_DATAEND_MASK)
            {
                pContext->ep0State = CSL_USB_EP0_IDLE;
            }
            /* else remain in rx state */
        }

You should see that this code will only be executed when the RX interrupt happens on EP0 and there is a data packet came in, so the USB_readEP0Buf() got called to read the data from the EP0 RX FIFO. The USB_readEP0Buf (defined in csl_usbAux.h) only sets the CSL_USB_PERI_CSR0_INDX_DATAEND_MASK when the reciving packet is the last packet:

if(pContext->cbOutEP0DataReceived == 0)
{
/* set DataEnd bit */
flag = CSL_USB_PERI_CSR0_INDX_DATAEND_MASK;
}

Then the " check if data end bit is set" is following immediately, so it should not be missed, unless there is a RX packet comes in before you check the DATAEND bit. In this case the DATAEND will be cleared automatically. Of course, this extreme case is out of the USB spec, but worth to check it out.

In summary, the DATAEND bit got set by CPU in three cases: sending last TX packet, got the last RX packet and sending TX zero length packet. It will be cleared after the TX packet is transmitted, or a new RX packet is received in FIFO. It is for EP0 only.

Ming

0 J-breeze over 5 years ago in reply to Ming Wei

Expert 1105 points

Hi Ming,

Thank you for your advice. I will check it out.

Best regards,
J-breeze

0 J-breeze over 5 years ago in reply to J-breeze

Expert 1105 points

Hi Ming,

I have questions before I check it out.

Q1) About "unless there is a RX packet comes in before you check the DATAEND bit. "

What kind of RX packet comes in? Is it for EP0 only?

Q2) About "this extreme case is out of the USB spec"

Could you please let me know which part of the usb standard applies?

Best regards,
J-breeze

0 J-breeze over 5 years ago in reply to J-breeze

Expert 1105 points

Hi,

I'd like to withdraw the Q1.
So, could you please answer the Q2? I'd like to make sure of it.

Best regards,
J-breeze

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TMS320C5535: When is the USB DataEnd bit cleared?