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TMS320C6678: Requirement of parameters for PDN analysis (power integrity) of 6678 multi-core processor

Part Number: TMS320C6678

Hi,

We are planning to use TI multicore DSP - TMS3206678. We need some information to do a proper AC power distribution network (PDN) analysis for power integrity. These information are not separately defined in the power calculation excel sheet provided by Texas Instruments. However, they are critical for the analysis.

1. Transceivers:
We need the transient current requirement per transceiver for the speeds designated for specific interfaces.  We also need the total voltage fluctuation that is allowed for ac transients.

 S.N.

Description

Imin (mA)

Imax (mA)

±ΔVoltage (mV)

1

VDDT2 (1V)

 

 

 

 

-          SGMII (1 Gb/s)

 

 

--

 

-          PCIe (5 Gb/s)

 

--

 

-          SRIO (5 Gb/s)

 

 

--

 

 

 

 

 

2

VDDR2 (1.5V)

 

 

 

 

-          PCIe (5 Gb/s)

 

 

--

 

 

 

 

 

3

VDDR3 (1.5V)

 

 

 

 

-          SGMII (1 Gb/s)

 

 

--

 

 

 

 

 

4

VDDR4 (1.5V)

 

 

 

 

-          SRIO (5 Gb/s)

 

 

--

2. PLL Supplies:

S.N.

Description

Imin (mA)

Imax (mA)

±ΔVoltage (mV)

1

AVDDA1

 

 

 

2

AVDDA2

 

 

 

3

AVDDA3

 

 

 

3. Package RLC parameters:

We need the following parameters - On-die capacitance (Codc), on-die resistance (Rodr), overall package series inductance (Lpkg), and overall package series resistance (Rpkg).

S.N.

Voltage Rail

Codc [nF]

Rodr [mΩ]

Lpkg [nH]

Rpkg [mΩ]

1

CVDD

 

 

 

 

2

CVDD1

 

 

 

 

3

DVDD18

 

 

 

 

4

DVDD15

 

 

 

 

Thanks,

Binayak

  • Binayak,

    We do not have that detail available.  We understand that that information is needed to perform a detailed an precise PDN analysis.  Instead we have provided power supply and filtering recommendations in our Hardware Design Guide for KeyStone I Devices Application Report SPRABI2C in chapter 2.

    Tom

  • Hello Tom,

    I have posted my initial question after going through all of the documents that TI has provided in this matter. I have some follow-up questions to your answer.

     When you say "we don't have the details available" - 

    [a] Does it mean that the details exist but not available in the public domain? In that case, contacting our local FAE and signing NDA should be sufficient to get hold of these data.

    [b] If the data is actually not available to the TI team also (meaning that the device characterization has not been done till now), I would like to know on what basis TI is providing the  power supply and filtering guidelines. For example, there is NO WAY of recommending a filtering circuit for transceiver power rails if TI doesn't know how much current each transceiver consumes.

    Thanks,

    Binayak

  • Binayak,

    We do not have the information requested at that level of precision or granularity.  Getting an NDA will not release additional detail.  Recommendations provided are based on simulations at the IP and chip levels.  The C6678 is a mature device with many design-ins.  The information provided is sufficient for you to successfully implement a robust board.

    Tom

  • Tom,

    I'm little confused. 

    [a] How were you able to come up with the filtering circuits for powering sensitive PLL and transceiver circuits without knowing what to filter? You would need to know the noise sensitivity of the DUT (PLL/transceiver) and some information about the frequency content of the transient current through it to design any filter.

    [b] The supplies for the PLLs and transceiver circuits have been derived from the main voltage rails that consume comparatively large transient currents and are generally noisy. If we want to power the transceiver and PLL circuits separately instead of deriving them from the main voltages (CVDD1, DVDD15, DVDD18) using ferrite beads, what guidelines does TI provide? 

    Thanks,

    Binayak

  • Binayak,

    Like I said, we do not have the information requested at that level of precision or granularity.  IP comes from multiple vendors.  The information provided for some of the IPs at the time this chip was designed did not contain the information that you are requesting.  Some of them simply provided filter circuits same as we are recommending to you.

    Providing low-noise power sources for the PLLs and transceivers will always provide better performance but that is beyond the requirements that are stated.  This improvement is not characterized so we cannot state how much it will help.  Therefore, we do not provide this in our guidance.

    Tom

  • Hi Tom,

    So this is what I have understood. Kindly correct me if I am wrong.

    I believe that the IP that you are referring to is the hardware IP of the asic subcircuits inside the DSP. Say for example, if the IP for the transceiver circuit section was provided by a third party vendor, then along with this circuit IP, they also provided what the on-board filtering circuit should be.

    Am I correct in this understanding?

     

    Thanks,

    Binayak

     

     

  • Binayak,
    That is correct.
    Tom