RTOS/AM5728: Data Corruption over SPI read

Hi,

I am reading with 1s delay from fpga.  Correct value is 0x11aa11aa.

Few of the corrupt values are 0x23542356, 0x234a11aa, 0x23542354, 0x2354236a, 0x23542352.

I am probing both, as you can see attached img.

I don`t logic analyzer currently available, CRO is the only option.

Thanks & Regards,

Raksha

Hi,

Please note here that data corruption seems to be happening while doing SPI_read only. SPI_write works perfectly and slave device is getting configured properly.

Thanks & Regards,

Raksha

Hi,

1) We have already tried with TI`s mode 0 & mode 1 i.e., with PHA0 & POL0 and PHA1 & POL1. Both seems to have this read issue.

2) Duty Cycle is as default 50-50. Trying to change and see the effect.

3) PFA, capture with correct value of 0x11aa11aa & corrupt value as 0x23542356 (first & second img resp).

Thanks & Regards,

Raksha

Hi,

I tried with different range of frequencies from 5khz, 10khz, 100khz, 300khz, 350khz, 1Mhz, 1.5Mhz, 5Mhz, 10Mhz, 15Mhz.

Data us getting corrupted, less number of times in 350khz and 1,5Mhz, most of the times in 10Mhz and 15Mhz.

Please note hear in all this frequency range I am able to do SPI_write successfully to configure the FPGA, only read is failing.

Thanks & Regards,

Raksha

memory_spi.datHi,

here am attaching the SPI register values that we use to configure

regards,

Ranganath

Hi,

1) We have checked with other devices on different buses, spi1 & spi2 respectively. There was no clock drift observed and we are reading correct data continuously. Will try out same in loopback.

2) Data corruption is happening at all mentioned frequencies but less frequently at 350Khz & 1.5Mhz.

3) We are not seeing any shift while writing.

4) Please find attached SPI dumps starting from SPI bus3 addr 0x480B8000 for working and non-working case.

memory_spi3_11aa11aa.dat

memory_spi3_.dat

Thanks & Regards,

Raksha

Hi Yordan,

is that possible to test this loop back on AM5728??

thanks

Ranganath

Hi,

we tried the same loopback example for SPI1 and SPI2 they are working fine.

And we tried with different polarity and phase  for SPI3, we are getting the corrupted data over SPI3.

regards,

Ranganath

MCSPI_BasicLoopbackExample.zipHi Yordan,

we have tested the loopback on SPI3, it is failing continously oon am5728. Please can you verify

and test it from your side as soon as possible. It  requires a urgent attention.

here am attaching the project file which we are testing loopback example.

here showing the the spi3 sclk, miso, mosi and cs0 connected to the slave(FPGA).

HI,

we tried with the bit banging method for SPI_bus3 it is working fine with the same FPGA as slave.

but with the SPI driver it is inconsistent. how??

thanks

Ranganath

Hi,

we have verified with the IOSETS...we are configuring them as mentioned in the Table.

we have tested with frequency of 500hz to 30MHz, SPI3 read getting corrupted.

SPI2 bus is working fine.

Regards,

Ranganath

Hi Yordan,

we are doing pinmuxing for spi3 as follow,

regVal = 0xC0003;
((CSL_padRegsOvly)CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MCASP1_AXR10 =
regVal; /* D0 */

regVal = 0xC0003;
((CSL_padRegsOvly)CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MCASP1_AXR11 =
regVal; /* CS0 */

regVal = 0xC0003;
((CSL_padRegsOvly)CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MCASP1_AXR8 =
regVal; /* SCLK */

regVal = 0xC0003;
((CSL_padRegsOvly)CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_MCASP1_AXR9 =
regVal; /* D1 */

Also we are doing clock configuration for spi3 as follow,
/* MODULE CLOCK INIT FOR MCSPI3 */
timeout = SPI_TRANSACTION_TIMEOUT;
CSL_FINST(l4PerCmReg->CM_L4PER_MCSPI3_CLKCTRL_REG,
L4PER_CM_CORE_COMPONENT_CM_L4PER_MCSPI3_CLKCTRL_REG_MODULEMODE, ENABLE);

while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_MCSPI3_CLKCTRL_REG_IDLEST_FUNC !=
CSL_FEXT(l4PerCmReg->CM_L4PER_MCSPI3_CLKCTRL_REG,
L4PER_CM_CORE_COMPONENT_CM_L4PER_MCSPI3_CLKCTRL_REG_IDLEST))
{
timeout--;
if(timeout == 0)
{
Log_print0(Diags_USER1," : SPI module clock initialization failed");
break;
}
}
/* END OF MODULE CLOCK INIT FOR MCSPI3 */

is this what you are suggesting for ?"It is possible that the interface needs some loopback for clock re-sync " or anything else we have to do?

Thanks for your reply,
Ranganath

Hi Yordan,

Thanks for your replay. we are doing same thing what you suggested. we are using B12 SPi3_clk and already we are setting CTRL_CORE_PAD
_MCASP1_AXR8[bit 18]MCASP1_AXR8_INPUTENABLE as 1. It's not helping to solve the issue even for spi3 internal loopback test. 

we have already shared our spi3 loopback project code base. have you tested from your side spi3 internal loopback code for AM5728?

Thanks 

Ranganath

Hi Yordan,

Have you tested loop-back test for spi3 from your-side, please let me know.

thanks 

Ranganath

Part Number: AM5728

Tool/software: TI-RTOS

hi yordan,

we didn't get any response till now please let us know any progress from your side.

Hi,

we are still stuck in this issue, please look at this on high priority.

thanks 

Ranganath