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AM5728: Baremetal UART example /Interrupt

Part Number: AM5728

Hello.

Im working with idk AM5728. I want to use UART.3 to receive data. It worked successfully without interrupt. I tried to configure the RHR interrupt. I have used the main code in pdk_am57xx_1_0_11\packages\ti\csl\example\uart\uart_intr for enabling interrupt (I changed the parameters and addresses due to AM5728/IPU1/C0) and interrupt.h in pdk_am57xx_1_0_11\packages\ti\csl\arch\m4 for the interrupt functions.  but nothing happened.

I checked the registers through Memory browser. it seems that an interrupt is pending. The value in UART_IIR (0x4802 0008) shows that Rx_time out is pending. These are the values of my memory after receiving data.

Now i have some questions.

1. Some registers in datasheet have same addresses (like UART_IIR and UART_EFR). How is it possible, and how can i understand what register im checking in memory browser in CCS?

2. what is the difference of RHR interrupt and Rx time-out interrupt and when does Rx time-out interrupt happen?

3. Is it necessary to config interrupt priorities (because there is just one interrupt)? I didn't do anything in my code for this part and the function of  Intc_IntPrioritySet is empty.

4. The IPU can handle 80 interrupts Due to chapter 17 of datasheet (Interrupt controller): 16 internal and 64 external interrupts. How can I set the ISR for each of them.

5. What should i do to config NVIC in IPU?

5. Can I use CMSIS library for my purpose? If i can, how?

6. Is there any bare metal example for UART (with interrupt) or for using NVIC?

Here is my whole project. Could you please take a look at my code? 

uart_interrupt_m4_BareMetal.rar

Any help regarding this issue would be greatly appreciated. Thank you

  • Ali,
    Thanks for your post, due the holidays our response may be delayed.

    Thanks,

    Catalog Processors

  • ali,

    1. Register access depends on the register access mode, although register access modes are not correlated to functional mode selection. Three different modes are available:
    • Operational mode
    • Configuration mode A
    • Configuration mode B
    see TRM 24.3.4.7.1 Register Access Modes

    2. RHR interrupt source - DRDY (data ready) (FIFO disabled), RX FIFO above trigger level (FIFO enabled)
    Rx Time-out interrupt source - stale data in Rx FIFO, refer to e2e.ti.com/.../44142

    3. Not necessary.

    4. You can configure the mapping of device interrupts to IRQ_CROSSBAR inputs using CSL_xbarIrqConfigure() API.

    5. Refer to UartINTCConfigure() in uart_intr\main.c

    5. not recommended.

    6. The closest example is the one you referred to: ti\csl\example\uart\uart_intr

    Regards,
    Garrett
  • Ali,

    Is there any reason that you don`t want to use the UART LLD provided in the Processor SDK RTOS. The driver is supported in polling, interrupt mode and also supports DMA mode of operation and works in both the bare-metal and rtos environment. It is support on all cores on the AM57x device.

    We highly recommend that you utilize the driver for your development rather than trying to build your own driver for a peripheral like UART.

    Regards,
    Rahul

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  • In reply to Rahul Prabhu:

    Yes. Because of some reasons i need a bare metal code. I need a reference to know how to configure the ISR functions. Is there any Reference?
  • In reply to ali shayei:

    uart_intr is the only bare-metal CSL example that we have in the Processor SDK RTOS that shows how the interrupts need to be configured. The details for TDA2xx also applies to AM57xx devices as those devices are superset devices with same memory and interrupt architecture that include some vision accelerators that are used for the automotive applications. The UartINTCConfigure is the function in that example that shows this configuration for UART1 for TDA2xx and UART3 for TDA3xx devices.

    In addition, you can also refer to the UART_open API for general guidance for interrupt configuration for the SOC but that API is common API for arm, dsp and m4 on the device so device specific detail like crossbar configuration needs to be managed from the application level.

    Regards,
    Rahul

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