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AM5728: PCIe IATU target address register change

Genius 17785 points

Replies: 5

Views: 102

Part Number: AM5728

Hi 

Like to understand when can the reg_target_address be changed when sending data from the DDR3 to the PCIe bus? The reason being i need to transfer more than 256MB data to the PCIe bus using the IATU, to be able to do that i need to change the reg_target_address. Can we change it on the fly or have to wait until it completes all the transfers? If that is the case how can we know when all the transfers are done? 

So if i am using the EDMA engine to transfer 4K of data from DDR3 to PCIe SS1 address 0x20000000  and have the IATU enabled. I assume once the EDMA is completed i can change the reg_target_address to a different PCIe bus address and start the EDMA the next clock? If that is the case then it sounds like the address translation is done on the fly.

Thanks


 
  • Mohsen,

    Which OS are you using?

  • In reply to -DK-:

    They are running Linux on the ARM. TI Rtos on the DSP.


     
  • Guru 54860 points

    In reply to Mohsen Khayami:

    Mohsen,

    If you are doing a transfer from the DDR3 to the PCIe bus over 256MB:

    If you are using CPU, the code more like this:
    *(unsigned int *)x02000_0000 = *(unsigned int *)0x8000_0000
    *(unsigned int *)x02000_0004 = *(unsigned int *)0x8000_0004
    ....
    *(unsigned int *)x02000_0000 = *(unsigned int *)0x9000_0000 //passing 256MB
    *(unsigned int *)x02000_0004 = *(unsigned int *)0x9000_0004
    ....

    Each time you change the SRC/DST address, correct?

    If you are using EDMA, the code more like this:
    EDMA_SRC = 0x8000_0000
    EDMA_DST = 0x2000_0000
    acnt, bcnt and ccnt for 256MB.

    After the transfer, you do the next
    EDMA_SRC = 0x9000_0000
    EDMA_DST = 0x2000_0000
    acnt, bcnt and ccnt for 256MB.

    So the PCIE bus address will always starts at 0x2000_0000.
    1) You can enable OB translation, first time say you translation 0x2000_0000 to 0xa000_0000, next time you translation to 0xb000_0000. Then in the receive side, the IATU maps 0xa000_0000 into SOC internal address 1. IATU maps 0xb000_0000 into address 2. Doing so the change is sending side, you need to wait the transfer finish before changing the OB from 0xa000_0000 to 0xb000_0000.

    2) Or, you can keep the PCIE OB translation the same, e.g, it always generates address 0xa000_0000, but change the receive side IB translation. Say, first time 0xa000_0000 maps to SOC internal address 1, next time 0xa000_0000 maps to internal address 2. You also need to make the change only after the transfer finished.

    How do you know the transfer finished? Either read back the last one you send to make sure it is landed, or when the receive side got all the data, it sends a PCIE interrupt to sender. Or in EDMA case, there is transfer completion interrupt.

    Regards, Eric
  • In reply to lding:

    Hi Eric
    Thanks for the reply, I am worried about the internal fifo for the outbound. Even if the EDMA is done it does not mean the translation has been completed because of the below statement in the TRM.

    PCIe controller maximum outbound payload size is 64 Bytes (the L3 Interconnect PCIe1/2 target
    ports split bursts of size > 64 Bytes to the into multiple 64 Byte bursts). Only bursts of incremental
    type (INCR) are supported on the PCIe controller slave port.

    sounds like the only way to make sure that the transfer is done by reading the other side and make sure the data got there. It would be good to know if there is an interrupt that says the transfer has completed but i can't see one.

    Also how would the other side know it has gotten all the data?

    Thanks

     
  • Guru 54860 points

    In reply to Mohsen Khayami:

    Hi,

    The received side knows the data come in only if it knows what data pattern it is expected or data changed. Then the received side can generate an PCIE interrupt to sender to tell that data is received. The PCIE data write transaction itself doesn't generate any interrupt.

    If you use EDMA, there are intermediate transfer interrupt and Transfer complete interrupt to choose from. The former is generated when the transfer is completed.

    Regards, Eric