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Linux/AM5718: AM5718 custom board interfacing with camera sensor

Part Number: AM5718

Tool/software: Linux

Hello Margarita,

Now we must need to change the cal driver for line by line instead of frame by frame.
so please guide us for required modification for line by line implementation.
this is the our last hope to increase the fps for our end application goal.

Thanks,

Simit

  • Hi Simit,

    Line by line capture is not supported by CAL.

    Regards,
    Manisha
  • Hi Manisha,

    I understand that. But what needs to be done if we want to add support.

    Will you please provide us the required document so we can customize the code and can test.

    See it is possible with other sensor so we just want to add this feature by our own but we need the require document for cal and other stuff.

    If you provide us then it will be great and we can procced further.

    Thanks,

    Simit

  • Hi Simit,

    Since this is not supported use case, we haven't evaluated if it possible by the device or how to enable it. All the information about CSI-2/CAL IP is in AM57x Technical Reference Manual. Please go through the TRM.

    Regards,
    Manisha
  • Hi Manisha,


    We will talk for line by line support later.

    Please provide us the flow diagram/low level Architecture Diagram of exist cal driver so i can understand quickly and do the next steps for that.

    Thanks,

    Simit

  • Hi Simit,

    Unfortunately we don't have such a document to share. You will need to study the driver code.

    Regards,
    Manisha
  • Hi Manisha,

    Please provide us the details of below Register.
    CAL_CSI2_PHY_REG10

    We checked in TRM but still we didn't get any clue of this register.

    Thanks,

    Simit

  • Hi Simit,

    That register is only applicable to PG 1.0 device to handle LDO errata workaround. It is not applicable to PG 2.0 silicon. I am assuming you will be using PG 2.0 silicon.

    Regards,
    Manisha
  • Hi Manisha,

    Here are the couple of queries that i have listed out would you please look at this and let me know the answers.

    1) How we will check taht our PG version is 1.0 or 2.0?
    2) what is the OCP Port in Camera Interface Subsystem section?
    3) what is the OCPC Port in Camera Interface Subsystem section?
    4) what is the OCPO Port in Camera Interface Subsystem section?

    Thanks,

    Simit

  • Hi Manisha,

    This is just Gentle reminder.

    Thanks,

    Simit

  • Hi Simit,

    In the CAL Linux driver we use a specific compatible string to show PG1.0 because from the driver level framework we cannot access the device level information at run-time as the mach-omap2 functions needed to get to this info are not accessible for driver code.

    At any rate on a booted Linux system you can see the device Id and revision in the kernel log as it is detected early on in the boot process. If you want to know how to access and decipher the device id and revision you can start by taking a look at dra7xxx_check_revision() in arch/arm/mach-omap2/id.c.


    OCP is the bus architecture so these only refer to the various access point between the CAL h/w and the system bus. I don't think you need to worry about these.

    If search OCP in the TRM you'll quickly see that is it referenced everywhere.

    Regards,
    Manisha
  • Dear Manisha,

    Thanks for your reply.

    We have added "CAL_LINE_NUMBER_EVT" register in "enable_irqs" function to get interrupt on every 48 lines as per below.

     

    /*

    * Enable the expected IRQ sources

    */

    static void enable_irqs(struct cal_ctx *ctx)

    {

    u32 val;

    printk("%d - %s()\n", __LINE__, __FUNCTION__ );

    /* Enable IRQ_WDMA_END 0/1 */

    reg_write_field(ctx->dev,

    CAL_HL_IRQENABLE_SET(2),

    CAL_HL_IRQ_ENABLE,

    CAL_HL_IRQ_MASK(ctx->csi2_port));

    /* Enable IRQ_WDMA_START 0/1 */

    reg_write_field(ctx->dev,

    CAL_HL_IRQENABLE_SET(3),

    CAL_HL_IRQ_ENABLE,

    CAL_HL_IRQ_MASK(ctx->csi2_port));

    /* Todo: Add VC_IRQ and CSI2_COMPLEXIO_IRQ handling */

    reg_write(ctx->dev, CAL_CSI2_VC_IRQENABLE(1), 0xFF000000);

    //===========Added by Nikunj======================================//

    val = reg_read(ctx->dev, CAL_LINE_NUMBER_EVT);

    set_field(&val, 0, CAL_LINE_NUMBER_EVT_CPORT_MASK);

    set_field(&val, 48, CAL_LINE_NUMBER_EVT_MASK); //48 Lines

    reg_write(ctx->dev, CAL_LINE_NUMBER_EVT, val);

    ctx_dbg(3, ctx, "CAL_LINE_NUMBER_EVT= 0x%08x\n",reg_read(ctx->dev, CAL_LINE_NUMBER_EVT));

    //End===========Added by Nikunj======================================//

    ctx_dbg(3, ctx, "CAL_CSI2_VC_IRQENABLE(1) = 0x%08x\n",reg_read(ctx->dev, CAL_CSI2_VC_IRQENABLE(1)));

    }

     

    still, we are not getting any interrupt event after adding this register so can you please help me to just guide me for am I missing anything?


    Thanks & Best Regards,
    Nikunj Patel

     

  • Hi Nikunj,

    You have configured the LINE_NUMBER_EVT trigger value, now you also need to enable the related IRQ bit in CAL_HL_IRQENABLE_SET as well.

    Unfortunately that bit is not documented in the TRM. LINE_NUMBER_IRQ is bit 8 of the CAL_HL_IRQ*0 register.
    In your ‘enable” code below, you would need to add something like this:

    enable_irqs():

    reg_write_field(ctx->dev,
    CAL_HL_IRQENABLE_SET(0),
    CAL_HL_IRQ_ENABLE,
    BIT_MASK(8));


    And similar in disable_irqs():

    reg_write_field(ctx->dev,
    CAL_HL_IRQENABLE_CLR(0),
    CAL_HL_IRQ_CLEAR,
    BIT_MASK(8));

    Regards,
    Manisha
  • Hi Manisha,

    Thanks for your reply.

    We have modified code as below but still we didnot get interrupt after 48 line so please look and suggest us if we miss anything. As per your last reply we feel still you have more details document then TRM so please share with us. if it need NDA so we are ready for that.

    /*

    * Enable the expected IRQ sources

    */

    static void enable_irqs(struct cal_ctx *ctx)

    {

    u32 val;

    //===========Added by Nikunj======================================//

    val = reg_read(ctx->dev, CAL_LINE_NUMBER_EVT);

    set_field(&val, ctx->csi2_port, CAL_LINE_NUMBER_EVT_CPORT_MASK);

    //~ set_field(&val, 0, CAL_LINE_NUMBER_EVT_CPORT_MASK);

    set_field(&val, 48, CAL_LINE_NUMBER_EVT_MASK); //48 Lines

    reg_write(ctx->dev, CAL_LINE_NUMBER_EVT, val);

    ctx_dbg(3, ctx, "CAL_LINE_NUMBER_EVT= 0x%08x\n",reg_read(ctx->dev, CAL_LINE_NUMBER_EVT));

    //End===========Added by Nikunj======================================//

    printk("%d - %s()\n", __LINE__, __FUNCTION__ );

    /* Enable IRQ_WDMA_END 0/1 */

    reg_write_field(ctx->dev,

    CAL_HL_IRQENABLE_SET(2),

    CAL_HL_IRQ_ENABLE,

    CAL_HL_IRQ_MASK(ctx->csi2_port));

    /* Enable IRQ_WDMA_START 0/1 */

    reg_write_field(ctx->dev,

    CAL_HL_IRQENABLE_SET(3),

    CAL_HL_IRQ_ENABLE,

    CAL_HL_IRQ_MASK(ctx->csi2_port));

    reg_write_field(ctx->dev,

    CAL_HL_IRQENABLE_SET(0),

    CAL_HL_IRQ_ENABLE,

    BIT_MASK(8));

    /* Todo: Add VC_IRQ and CSI2_COMPLEXIO_IRQ handling */

    reg_write(ctx->dev, CAL_CSI2_VC_IRQENABLE(1), 0xFFFFFFFF); // modified by Nikunj

    ctx_dbg(3, ctx, "CAL_CSI2_VC_IRQENABLE(1) = 0x%08x\n",reg_read(ctx->dev, CAL_CSI2_VC_IRQENABLE(1)));

    }

    static void disable_irqs(struct cal_ctx *ctx)

    {

    printk("%d - %s()\n", __LINE__, __FUNCTION__ );

    /* Disable IRQ_WDMA_END 0/1 */

    reg_write_field(ctx->dev,

    CAL_HL_IRQENABLE_CLR(2),

    CAL_HL_IRQ_CLEAR,

    CAL_HL_IRQ_MASK(ctx->csi2_port));

    /* Disable IRQ_WDMA_START 0/1 */

    reg_write_field(ctx->dev,

    CAL_HL_IRQENABLE_CLR(3),

    CAL_HL_IRQ_CLEAR,

    CAL_HL_IRQ_MASK(ctx->csi2_port));

    /* Todo: Add VC_IRQ and CSI2_COMPLEXIO_IRQ handling */

    reg_write_field(ctx->dev,

    CAL_HL_IRQENABLE_CLR(0),

    CAL_HL_IRQ_CLEAR,

    BIT_MASK(8));

    reg_write(ctx->dev, CAL_CSI2_VC_IRQENABLE(1), 0);

    }

    Thanks & Best Regards,

    Nikunj Patel

  • Gentle reminder,

    Thanks & Best Regards,
    Nikunj Patel
  • Dear Manisha,

    Please provide us the support for why there was no getting any interrupt after 48 lines completed after applying our changes?

    Also, I did one test with the whole (0-31) bits enabled for interrupt and still I did not get any extra interrupt.

    still we are missing something?

    This is the major issue which is directly affecting our final application right now and we are stuck up with this issue. I did testing with below changes but still, I am not able to get any interrupt after completion of 48 lines.

    Add " set_field(&val, 1, CAL_WR_DMA_CTRL_ICM_PSTART_MASK)" line in cal_wr_dma_config() functions.
    Add  belows lines in cal_wr_dma_config functions.
                reg_write_field(ctx->dev,
                CAL_WR_DMA_OFST(ctx->csi2_port),
                CAL_WR_DMA_OFST_CIRC_MODE_SIXTYFOUR,
                CAL_WR_DMA_OFST_CIRC_MODE_MASK); 

    Thanks & Best Regards,
    Nikunj Patel