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RTOS/AM5728: Synchronizing DMA callbacks for multiple MCASP buses

Jimit Patel
Intellectual 570 points
Part Number: AM5728

Tool/software: TI-RTOS

I am using TI Linux and RTOS SDK v4.3 for AM5728 - Linux on A15, TI-RTOS on DSP and M4 cores. 

I am using MCASP 3, 4, and 5 buses on the DSP. The clock is set to internal for all MCASP buses, i.e. DSP is the clock master. The audio from all the buses runs through the mixer and other audio processing code on the DSP. It's required that the DMA callbacks from all three MCASP buses synchronize but I am seeing delays in the callbacks from different buses. All TX and RX buffers for MCASP buses are being submitted simultaneously, but semaphore posts from the callback are skewed by ~1.5 to 2ms. Callbacks for RX and TX for same MCASP bus is within 120 to 150usec, but there's more than 1.5ms offset between the callbacks between different MCASP buses. Is there any way I can reduce the latencies observed?

  • 0
    TI__Guru* 95265 points
    Hi,

    Can you point out what MCASP test example in PRSDK RTOS you tested the callback?

    Regards, Eric
  • 0 in reply to lding
    Intellectual 570 points

    Hi Eric,

    I have based the code on the device loopback example project. This is my setup for MCASP buses - 

    { /* MCASP3_TX */
    0xFFFFFFFF, // MCASP_TXMASK
    0x000180F0, // MCASP_TXFMT
    0x00000413, // MCASP_TXFMCTL
    0x000000FF, // MCASP_TXTDM
    0x0000000F, // MCASP_EVTCTLX
    0x000001FF, // MCASP_TXSTAT
    0x00000000, // MCASP_XEVTCTL
    {
    0x00000020, // MCASP_ACLKXCTL
    0x0000800F, // MCASP_AHCLKXCTL
    0x00000000 // MCASP_TXCLKCHK
    }
    },
    { /* MCASP3_RX */
    0xFFFFFFFF, // MCASP_RXMASK
    0x000180F0, // MCASP_RXFMT
    0x00000412, // MCASP_RXFMCTL
    0x000000FF, // MCASP_RXTDM
    0x0000000B, // MCASP_EVTCTLR
    0x000001FF, // MCASP_RXSTAT
    0x00000000, // MCASP_REVTCTL
    {
    0x00000020, // MCASP_ACLKRCTL
    0x0000800F, // MCASP_AHCLKRCTL
    0x00000000 // MCASP_RXCLKCHK
    }
    },
    { /* MCASP4_TX */
    0xFFFFFFFF, // MCASP_TXMASK
    0x00018070, // MCASP_TXFMT
    0x00000113, // MCASP_TXFMCTL
    0x00000003, // MCASP_TXTDM
    0x0000000F, // MCASP_EVTCTLX
    0x000001FF, // MCASP_TXSTAT
    0x00000000, // MCASP_XEVTCTL
    {
    0x00000025, // MCASP_ACLKXCTL
    0x0000807F, // MCASP_AHCLKXCTL
    0x00000000 // MCASP_TXCLKCHK
    }
    },
    { /* MCASP4_RX */
    0xFFFFFFFF, // MCASP_RXMASK
    0x00018070, // MCASP_RXFMT
    0x00000112, // MCASP_RXFMCTL
    0x00000003, // MCASP_RXTDM
    0x0000000B, // MCASP_EVTCTLR
    0x000001FF, // MCASP_RXSTAT
    0x00000000, // MCASP_REVTCTL
    {
    0x00000025, // MCASP_ACLKRCTL
    0x0000807F, // MCASP_AHCLKRCTL
    0x00000000 // MCASP_RXCLKCHK
    }
    },
    { /* MCASP5_TX */
    0xFFFFFFFF, // MCASP_TXMASK
    0x00018070, // MCASP_TXFMT
    0x00000113, // MCASP_TXFMCTL
    0x00000003, // MCASP_TXTDM
    0x0000000F, // MCASP_EVTCTLX
    0x000001FF, // MCASP_TXSTAT
    0x00000000, // MCASP_XEVTCTL
    {
    0x00000025, // MCASP_ACLKXCTL
    0x0000807F, // MCASP_AHCLKXCTL
    0x00000000 // MCASP_TXCLKCHK
    }
    }

    { /* MCASP3_TX */
    1,
    { Mcasp_SerializerNum_0 },
    &mcasp_setup[MCASP3_TX],
    TRUE,
    Mcasp_OpMode_TDM,
    Mcasp_WordLength_32,
    NULL,
    0,
    NULL,
    (Mcasp_GblCallback)M3_GblErrXmt,
    8,
    Mcasp_BufferFormat_1SER_MULTISLOT_INTERLEAVED,
    TRUE,
    8,
    TRUE,
    Mcasp_WordBitsSelect_MSB
    },
    { /* MCASP3_RX */
    1,
    { Mcasp_SerializerNum_1 },
    &mcasp_setup[MCASP3_RX],
    TRUE,
    Mcasp_OpMode_TDM,
    Mcasp_WordLength_32,
    NULL,
    0,
    NULL,
    (Mcasp_GblCallback)M3_GblErrRcv,
    8,
    Mcasp_BufferFormat_1SER_MULTISLOT_INTERLEAVED,
    TRUE,
    8,
    TRUE,
    Mcasp_WordBitsSelect_MSB 
    },

    { /* MCASP4_TX */
    1,
    { Mcasp_SerializerNum_0 },
    &mcasp_setup[MCASP4_TX],
    TRUE,
    Mcasp_OpMode_TDM,
    Mcasp_WordLength_16,
    NULL,
    0,
    NULL,
    (Mcasp_GblCallback)M4_GblErrXmt,
    2,
    Mcasp_BufferFormat_1SER_MULTISLOT_INTERLEAVED,
    TRUE,
    4,
    TRUE,
    Mcasp_WordBitsSelect_MSB
    },
    { /* MCASP4_RX */
    1,
    { Mcasp_SerializerNum_1 },
    &mcasp_setup[MCASP4_RX],
    TRUE,
    Mcasp_OpMode_TDM,
    Mcasp_WordLength_16,
    NULL,
    0,
    NULL,
    (Mcasp_GblCallback)M4_GblErrRcv,
    2,
    Mcasp_BufferFormat_1SER_MULTISLOT_INTERLEAVED,
    TRUE,
    4, // was 2
    TRUE,
    Mcasp_WordBitsSelect_MSB
    },
    { /* MCASP5_TX */
    1,
    { Mcasp_SerializerNum_0 },
    &mcasp_setup[MCASP5_TX],
    TRUE,
    Mcasp_OpMode_TDM,
    Mcasp_WordLength_16,
    NULL,
    0,
    NULL,
    (Mcasp_GblCallback)M5_GblErrXmt,
    2,
    Mcasp_BufferFormat_1SER_MULTISLOT_INTERLEAVED,
    TRUE,
    4, 
    TRUE,
    Mcasp_WordBitsSelect_MSB
    }

    I am starting and priming all buses at same time.

  • 0 in reply to Jimit Patel
    TI__Guru** 114410 points
    Jimit,

    Is this also observed in standalone DSP application when Linux is not running on the A15 ? Please check out the setup and report if the same issue also observed on RTOS only environment running on the DSP as power management in ARM Linux can some time cause latency issues on the slave cores.

    Regards
    Rahul
  • 0 in reply to Rahul Prabhu
    Intellectual 570 points

    Hi Rahul,

    I will have to get back to you on this. Currently, the DSP project has audio being streamed from Linux and going out on MCASP buses. I would have to edit the code to run it on RTOS-only environment.

    Thanks,

    Jimit