Linux/AM4378: u-boot not running DHCP, ethernet in half duplex mode

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Replies: 24

Views: 881

Part Number: AM4378

Tool/software: Linux

environment

Linux host ubuntu 16.04

SDK 4.03.0.5

U-Boot 2017.01-00458-gccd1c34

custom board loosely based on the am4378 gp evm

we've had some issues getting the board to come up but we did finally get u-boot to start and run. now i am trying to get dhcp to happen and it isn't.

-------------------------------------------------------------------------------------------------------------------------------

our u-boot environment output is:

=> pr
arch=arm
args_mmc=run finduuid;setenv bootargs console=${console} ${optargs} root=PARTUU}
baudrate=115200
board=UTI-board
board_name=UTI-board
boot_fdt=try
boot_fit=0
bootcmd=run findfdt; run getuenv; setenv autoload no;dhcp ;tftp ${loadaddr} zIm}
bootdelay=2
bootdir=/boot
bootenvfile=uEnv.txt
bootfile=zImage-am437x-evm.bin
bootm_size=0x10000000
bootpart=0:2
bootscript=echo Running bootscript from mmc${mmcdev} ...; source ${loadaddr}
console=ttyO0,115200n8
cpu=armv7
devtype=mmc
dfu_alt_info_emmc=rawemmc raw 0 3751936;boot part 1 1;rootfs part 1 2;MLO fat 11
dfu_alt_info_mmc=boot part 0 1;rootfs part 0 2;MLO fat 0 1;MLO.raw raw 0x100 0x1
dfu_alt_info_qspi=u-boot.bin raw 0x0 0x080000;u-boot.backup raw 0x080000 0x08000
dfu_alt_info_ram=kernel ram 0x80200000 0x4000000;fdt ram 0x80f80000 0x80000;ram0
dfu_bufsiz=0x10000
envboot=mmc dev ${mmcdev}; if mmc rescan; then echo SD/MMC found on device ${mm;
eth1addr=f0:b5:d1:3e:83:64
ethact=cpsw
ethaddr=f0:b5:d1:3e:83:62
fdt_addr_r=0x88000000
fdtaddr=0x88000000
fdtcontroladdr=9df111b8
fdtfile=am437x-UTI.dtb
finduuid=part uuid mmc ${bootpart} uuid
fit_bootfile=fitImage
fit_loadaddr=0x87000000
getuenv=setenv devnum ${mmcdev}; if mmc rescan; then if run loadbootenv; then r;
importbootenv=echo Importing environment from mmc${mmcdev} ...; env import -t $}
ip_method=dhcp
kernel_addr_r=0x82000000
loadaddr=0x82000000
loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenvfile}
loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr
loadfdt=load ${devtype} ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}
loadfit=run args_mmc; bootm ${loadaddr}#${fdtfile};
loadimage=load ${devtype} ${bootpart} ${loadaddr} ${bootdir}/${bootfile}
loadramdisk=load ${devtype} ${devnum} ${rdaddr} ramdisk.gz
mmcboot=mmc dev ${mmcdev}; setenv devnum ${mmcdev}; setenv devtype mmc; if mmc ;
mmcdev=0
mmcloados=run args_mmc; if test ${boot_fdt} = yes || test ${boot_fdt} = try; th;
mmcrootfstype=ext4 rootwait
mtdids=nand0=nand.0
mtdparts=mtdparts=nand.0:256k(NAND.SPL),256k(NAND.SPL.backup1),256k(NAND.SPL.ba)
nandargs=setenv bootargs console=${console} ${optargs} root=${nandroot} rootfst}
nandboot=echo Booting from nand ...; run nandargs; nand read ${fdtaddr} NAND.u-}
nandroot=ubi0:rootfs rw ubi.mtd=NAND.file-system,4096
nandrootfstype=ubifs rootwait=1
netargs=setenv bootargs console=${console} ${optargs} root=/dev/nfs nfsroot=${sp
netboot=echo Booting from network ...; setenv autoload no; dhcp; run netloadima}
netloadfdt=tftp ${fdtaddr} ${fdtfile}
netloadimage=tftp ${loadaddr} ${bootfile}
nfsopts=nolock,v3,tcp,rsize=4096,wsize=4096
partitions=uuid_disk=${uuid_gpt_disk};name=rootfs,start=2MiB,size=-,uuid=${uuid}
pxefile_addr_r=0x80100000
ramargs=setenv bootargs console=${console} ${optargs} root=${ramroot} rootfstyp}
ramdisk_addr_r=0x88080000
ramroot=/dev/ram0 rw
ramrootfstype=ext2
rdaddr=0x88080000
rootpath=/home/ULTRATEC/michael_j/ti-processor-sdk-linux-am437x-evm-04.03.00.05S
scriptaddr=0x80000000
serverip=192.168.61.105
soc=am33xx
static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off
stderr=serial@44e09000
stdin=serial@44e09000
stdout=serial@44e09000
update_to_fit=setenv loadaddr ${fit_loadaddr}; setenv bootfile ${fit_bootfile}
usbargs=setenv bootargs console=${console} ${optargs} root=${usbroot} rootfstyp}
usbboot=setenv devnum ${usbdev}; setenv devtype usb; usb start ${usbdev}; if usi
usbdev=0
usbroot=/dev/sda2 rw
usbrootfstype=ext4 rootwait
vendor=ti
ver=U-Boot 2017.01-00458-gccd1c34-dirty (Apr 03 2019 - 16:17:58 -0500)

Environment size: 5662/65532 bytes

-------------------------------------------------------------------------------------------------------------------------------

the pinmux for mii1 is:

static struct module_pin_mux mii1_pin_mux[] = {
{OFFSET(mii1_txen), MODE(0)}, /* MII1_TCTL */
{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RCTL */
{OFFSET(mii1_txd3), MODE(0)}, /* MII1_TD3 */
{OFFSET(mii1_txd2), MODE(0)}, /* MII1_TD2 */
{OFFSET(mii1_txd1), MODE(0)}, /* MII1_TD1 */
{OFFSET(mii1_txd0), MODE(0)}, /* MII1_TD0 */
{OFFSET(mii1_txclk), MODE(0)}, /* MII1_TCLK */
{OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RCLK */
{OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RD3 */
{OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RD2 */
{OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RD1 */
{OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RD0 */
{OFFSET(mii1_col), MODE(0) | RXACTIVE}, /* MII1_COL */
{OFFSET(mii1_crs), MODE(0) | RXACTIVE}, /* MII1_CRS */
{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
{-1},
};

-------------------------------------------------------------------------------------------------------------------------------

the ethernet setup in the board.c looks like:

#ifndef CONFIG_DM_ETH
#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
static void cpsw_control(int enabled)
{
/* Additional controls can be added here */
return;
}

static struct cpsw_slave_data cpsw_slaves[] = {
{
.slave_reg_ofs = 0x208,
.sliver_reg_ofs = 0xd80,
.phy_addr = 16,
},
{
.slave_reg_ofs = 0x308,
.sliver_reg_ofs = 0xdc0,
.phy_addr = 1,
},
};

static struct cpsw_platform_data cpsw_data = {
.mdio_base = CPSW_MDIO_BASE,
.cpsw_base = CPSW_BASE,
.mdio_div = 0xff,
.channels = 8,
.cpdma_reg_ofs = 0x800,
.slaves = 1,
.slave_data = cpsw_slaves,
.ale_reg_ofs = 0xd00,
.ale_entries = 1024,
.host_port_reg_ofs = 0x108,
.hw_stats_reg_ofs = 0x900,
.bd_ram_ofs = 0x2000,
.mac_control = (1 << 5),
.control = cpsw_control,
.host_port_num = 0,
.version = CPSW_CTRL_VERSION_2,
};
#endif


/*
* This function will:
* Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
* in the environment
* Perform fixups to the PHY present on certain boards. We only need this
* function in:
* - SPL with either CPSW or USB ethernet support
* - Full U-Boot, with either CPSW or USB ethernet
* Build in only these cases to avoid warnings about unused variables
* when we build an SPL that has neither option but full U-Boot will.
*/
#if ((defined(CONFIG_SPL_ETH_SUPPORT) || \
defined(CONFIG_SPL_USBETH_SUPPORT)) && \
defined(CONFIG_SPL_BUILD)) || \
((defined(CONFIG_DRIVER_TI_CPSW) || \
defined(CONFIG_USB_ETHER)) && !defined(CONFIG_SPL_BUILD))
int board_eth_init(bd_t *bis)
{
int rv;
uint8_t mac_addr[6];
uint32_t mac_hi, mac_lo;

/* try reading mac address from efuse */
mac_lo = readl(&cdev->macid0l);
mac_hi = readl(&cdev->macid0h);
mac_addr[0] = mac_hi & 0xFF;
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
mac_addr[4] = mac_lo & 0xFF;
mac_addr[5] = (mac_lo & 0xFF00) >> 8;

printf("Mac Addr = %x:%x:%x:%x:%x:%x\n", mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3], mac_addr[4], mac_addr[5]);

#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
if (!getenv("ethaddr")) {
puts("<ethaddr> not set. Validating first E-fuse MAC\n");
if (is_valid_ethaddr(mac_addr))
eth_setenv_enetaddr("ethaddr", mac_addr);
}

#ifndef CONFIG_SPL_BUILD
mac_lo = readl(&cdev->macid1l);
mac_hi = readl(&cdev->macid1h);
mac_addr[0] = mac_hi & 0xFF;
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
mac_addr[4] = mac_lo & 0xFF;
mac_addr[5] = (mac_lo & 0xFF00) >> 8;

if (!getenv("eth1addr")) {
if (is_valid_ethaddr(mac_addr))
eth_setenv_enetaddr("eth1addr", mac_addr);
}
#endif
writel(MII_MODE_ENABLE, &cdev->miisel);
cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_MII;
cpsw_slaves[0].phy_addr = 1;

rv = cpsw_register(&cpsw_data);
if (rv < 0) {
printf("Error %d registering CPSW switch\n", rv);
return rv;
}
#endif

return rv;
}
#endif
#endif

-------------------------------------------------------------------------------------------------------------------------------

the output of the u-boot when trying to dhcp is:

U-Boot SPL 2017.01-00458-gccd1c34-dirty (Apr 03 2019 - 16:17:58)
Trying to boot from MMC1
SPL: Please implement spl_start_uboot() for your board
SPL: Direct Linux boot not active!
reading u-boot.img
reading u-boot.img
reading u-boot.img
reading u-boot.img


U-Boot 2017.01-00458-gccd1c34-dirty (Apr 03 2019 - 16:17:58 -0500)

CPU : AM437X-GP rev 1.2
Model: TI AM437x UTI BOARD
DRAM: 512 MiB
Pinmux for MII1_COL: 40000
Board Init
Power Init
PMIC: TPS65218
NAND: 0 MiB
MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
reading uboot.env
Board late Init
Processes Called: 0
Net: Mac Addr = f0:b5:d1:3e:83:62
cpsw
Hit any key to stop autoboot: 0
## Error: "findfdt" not defined
reading uEnv.txt
717 bytes read in 4 ms (174.8 KiB/s)
Importing environment from mmc0 ...
link up on port 0, speed 100, full duplex
BOOTP broadcast 1
BOOTP broadcast 2
BOOTP broadcast 3
BOOTP broadcast 4
BOOTP broadcast 5
BOOTP broadcast 6
BOOTP broadcast 7
BOOTP broadcast 8
BOOTP broadcast 9
BOOTP broadcast 10
BOOTP broadcast 11
BOOTP broadcast 12
BOOTP broadcast 13
BOOTP broadcast 14
BOOTP broadcast 15
BOOTP broadcast 16
BOOTP broadcast 17
BOOTP broadcast 18
BOOTP broadcast 19
BOOTP broadcast 20
BOOTP broadcast 21
BOOTP broadcast 22
BOOTP broadcast 23
BOOTP broadcast 24
BOOTP broadcast 25
BOOTP broadcast 26
BOOTP broadcast 27
BOOTP broadcast 28
BOOTP broadcast 29

Retry time exceeded; starting again
link up on port 0, speed 100, full duplex
*** ERROR: `ipaddr' not set
link up on port 0, speed 100, full duplex
*** ERROR: `ipaddr' not set

when i wireshark the line there are no DHCP packets present

the PHY reset is high so it is not in reset

where else do i look to fix this?

24 Replies

  • so new day, new brain. i am starting to see some things that i didn't yesterday

    So we are trying to run in MII mode. our PHY is NOT a gigabit PHY, it is a DP83848M PHY

    i see that the pinmux options for these balls are GMII, RMII, and RGMII, but not MII

    so my question currently is: if we use this PHY in MII mode, are we guarantee'd to not be able to use ethernet?
  • In reply to cobsonchael:

    Hi,

    The AM437x parts only support MII so you should be to use the ethernet.

    Based on the console output the Ethernet link is being established but you are not seeing any packets come out on the interface, if my summary is correct. A quick review of the code looks like you are trying to use the second Ethernet interface on the board. Typically the TI boards use and only test the first port in u-boot. Is there a reason you are trying to use the second port? There maybe some significant code changes to implement using the second port in u-boot.

    Best Regards,
    Schuyler
  • In reply to Schuyler Patton:

    well we have the PHY connected to MII1 (which the EVM uses) and i didn't actively try to use anything but the default port.

    if you are talking about our PHY address our PHy chip should default to address 1 without any pullups/downs

    where in the code does it specify the port we are trying to use? according to the output we are trying to use port 0:
    "link up on port 0, speed 100, full duplex"

    in addition how should i set up for my board? should i set it up in the pinmux as RGMII but MII in the u-boot code or should i do it exactly like the EVM even though my phy doesn't support gigabit ethernet? does RGMII automatically scale down to normal MII? 

  • In reply to cobsonchael:

    any ideas?

  • In reply to cobsonchael:

    Hi,
    First I need apologize for the delay in responding.

    To answer your question, the pin mux needs to match between the PHY and the MAC, if your PHY is configured through HW strapping to be MII the MAC interface needs to be MII.

    Let's first double check that the PHY is seeing a link partner. Please do the following commands to output the state of link and the PHY:
    mii dump 1 0 - the one is PHY address 1
    mii dump 1 1

    Also please look at this register in the HW statistics block, we looking to see if the MAC thinks it sent packets.
    md.l 4a100934
    md.l 4a100938
    md.l 4a100964

    I will review the code a little bit more in the meantime.

    Regards,
    Schuyler
  • In reply to Schuyler Patton:

    output from mii dump 1 0:

    0. (3100) -- PHY control register --
    (8000:0000) 0.15 = 0 reset
    (4000:0000) 0.14 = 0 loopback
    (2040:2000) 0. 6,13 = b01 speed selection = 100 Mbps
    (1000:1000) 0.12 = 1 A/N enable
    (0800:0000) 0.11 = 0 power-down
    (0400:0000) 0.10 = 0 isolate
    (0200:0000) 0. 9 = 0 restart A/N
    (0100:0100) 0. 8 = 1 duplex = full
    (0080:0000) 0. 7 = 0 collision test enable
    (003f:0000) 0. 5- 0 = 0 (reserved)

    output from mii dump 1 1:
    1. (786d) -- PHY status register --
    (8000:0000) 1.15 = 0 100BASE-T4 able
    (4000:4000) 1.14 = 1 100BASE-X full duplex able
    (2000:2000) 1.13 = 1 100BASE-X half duplex able
    (1000:1000) 1.12 = 1 10 Mbps full duplex able
    (0800:0800) 1.11 = 1 10 Mbps half duplex able
    (0400:0000) 1.10 = 0 100BASE-T2 full duplex able
    (0200:0000) 1. 9 = 0 100BASE-T2 half duplex able
    (0100:0000) 1. 8 = 0 extended status
    (0080:0000) 1. 7 = 0 (reserved)
    (0040:0040) 1. 6 = 1 MF preamble suppression
    (0020:0020) 1. 5 = 1 A/N complete
    (0010:0000) 1. 4 = 0 remote fault
    (0008:0008) 1. 3 = 1 A/N able
    (0004:0004) 1. 2 = 1 link status
    (0002:0000) 1. 1 = 0 jabber detect
    (0001:0001) 1. 0 = 1 extended capabilities

    register values:
    md.l 4a100934 = 0
    md.l 4a100938 = 0
    md.l 4a100964 = 0

    so looks like it isn't putting out anything
  • In reply to cobsonchael:

    additional info, we do not have a RTC crystal on the board. would this have any effect on the ethernet?
  • In reply to cobsonchael:

    Hi,
    Thank you for posting the stats location registers and the MII registers.

    I agree that the MAC is not output putting packets. The MII registers indicate that there is a link between the PHY and the link partner so the conditions appear correct for packets to be transmitted.

    The RTC crystal is only needed to clock the RTC IP in the SOC and to my knowledge should not be needed for the Ethernet interface. For the custom board DTS file that have been done, what other included DTSI files have been modified?

    Best Regards,
    Schuyler
  • In reply to Schuyler Patton:

    we copied the 4378 gp evm dtsi file and renamed it am437x-UTI-u-boot.dtsi. i am unaware anywhere where it has to be "linked in" but i am likely wrong. i was told we just need to have the file exist and named similar to the dts file we use. it's contents are:

    /{
    ocp {
    u-boot,dm-spl;
    };
    };

    &uart0 {
    u-boot,dm-spl;
    };

    &mmc1 {
    u-boot,dm-spl;
    };

    &mac {
    u-boot,dm-spl;
    };

    &davinci_mdio {
    u-boot,dm-spl;
    };

    &cpsw_emac0 {
    u-boot,dm-spl;
    };

    &phy_sel {
    u-boot,dm-spl;
    };

    the portions of our DTS files that i think would make a difference are:


    mii_1_pins_default: mii_1_pins_default {
    pinctrl-single,pins = <
    AM4372_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE0) /* (D16) mii1_col.gmii1_col */
    AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* (B14) mii1_crs.gmii1_crs */
    AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE0) /* (B13) mii1_rx_er.gmii1_rxer */
    AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* (A13) mii1_tx_en.gmii1_txen */
    AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE0) /* (A15) mii1_rx_dv.gmii1_rxdv */
    AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* (D14) mii1_tx_clk.gmii1_txclk */
    AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE0) /* (D13) mii1_rx_clk.gmii1_rxclk */
    AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* (B15) mii1_txd0.gmii1_txd0 */
    AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* (A14) mii1_txd1.gmii1_txd1 */
    AM4372_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* (C13) mii1_txd2.gmii1_txd2 */
    AM4372_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* (C16) mii1_txd3.gmii1_txd3 */
    AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE0) /* (F17) mii1_rxd0.gmii1_rxd0 */
    AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* (B16) mii1_rxd1.gmii1_rxd1 */
    AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE0) /* (E16) mii1_rxd2.gmii1_rxd2 */
    AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE0) /* (C14) mii1_rxd3.gmii1_rxd3 */
    >;
    };

    /* Optional sleep pin settings. Must manually enter values in the below skeleton. */
    mii_1_pins_sleep: mii_1_pins_sleep {
    pinctrl-single,pins = <
    AM4372_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE0) /* (D16) mii1_col.gmii1_col */
    AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* (B14) mii1_crs.gmii1_crs */
    AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE0) /* (B13) mii1_rx_er.gmii1_rxer */
    AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* (A13) mii1_tx_en.gmii1_txen */
    AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE0) /* (A15) mii1_rx_dv.gmii1_rxdv */
    AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* (D14) mii1_tx_clk.gmii1_txclk */
    AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE0) /* (D13) mii1_rx_clk.gmii1_rxclk */
    AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* (B15) mii1_txd0.gmii1_txd0 */
    AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* (A14) mii1_txd1.gmii1_txd1 */
    AM4372_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* (C13) mii1_txd2.gmii1_txd2 */
    AM4372_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* (C16) mii1_txd3.gmii1_txd3 */
    AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE0) /* (F17) mii1_rxd0.gmii1_rxd0 */
    AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* (B16) mii1_rxd1.gmii1_rxd1 */
    AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE0) /* (E16) mii1_rxd2.gmii1_rxd2 */
    AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE0) /* (C14) mii1_rxd3.gmii1_rxd3 */
    >;
    };

    mdio_1_pins_default: mdio_1_pins_default {
    pinctrl-single,pins = <
    AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* (B17) mdio_clk.mdio_clk */
    AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | MUX_MODE0) /* (A17) mdio_data.mdio_data */
    >;
    };

    /* Optional sleep pin settings. Must manually enter values in the below skeleton. */
    mdio_1_pins_sleep: mdio_1_pins_sleep {
    pinctrl-single,pins = <
    AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* (B17) mdio_clk.mdio_clk */
    AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE0) /* (A17) mdio_data.mdio_data */
    >;
    };
    ----------------------------------------------------------
    &mac {
    slaves = <1>;
    pinctrl-names = "default", "sleep";
    pinctrl-0 = <&mii_1_pins_default>;
    pinctrl-1 = <&mii_1_pins_sleep>;
    status = "okay";
    };

    &davinci_mdio {
    pinctrl-names = "default", "sleep";
    pinctrl-0 = <&mdio_1_pins_default>;
    pinctrl-1 = <&mdio_1_pins_sleep>;
    status = "okay";
    };

    &cpsw_emac0 {
    phy_id = <&davinci_mdio>, <0>;
    phy-mode = "mii";
    };
  • In reply to cobsonchael:

    does the ethernet code use the SYNCTIMER?

    since we do not have an RTC crystal and the default clock for SYNCTIMER is the RTC crystal (figure 6.22, Table 6-176 spruhl7h) is it possible it is breaking the system for packet time stamps?