Hi Team,
In our ongoing design based on AM6548 SoC, we are planning to support USB3.1 interface on SERDES lanes to expansion connector. We have below queries:
1. We have routed the SERDES trace in the microstrip, with 90E differential impedance controlled. To achieve this, we have considered 4.2 mils trace width with 4.4 mil trace separation, referring to immediate ground plane(5 mil distant from the top layer). In the reference EVM design, we are observing layer 4 has been taken as reference plane for SERDES with 10.5mil trace width, 5 mil separation. Please let us know if there are any concerns.
Could you please let us know if there is a requirement for wider trace width for SERDES routing or if there is any requirement for tightly coupled differential routing.
2. Kindly note that, we have placed ac coupling caps closer to the SoC pins, with void in the reference plane underneath. Do we have to consider any reference plane for ac caps.
3. Please let us know if there is any specific recommendations to the SERDES routing.
Regards
Sushruta
