This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

RTOS/AM5726: SPI4 DMA configuration

Part Number: AM5726
Other Parts Discussed in Thread: SYSBIOS

Tool/software: TI-RTOS

HI!

We are using two CANFD controllers connected to SPI channel 2 and 4.

The SPI channel 2 works fine using DMA transfers, but for SPI channel 4 we need to configure the XBAR.

We have got stuck here, and can't figure how to configure the XBAR. Can we get some help how to use the DMA for this channel.

It's very important to get it up running due to performence issues.

We are using CCS-Studio (8.3)

SYSBIOS: version (bios_6_70_00_21)  and xdctools (3_50_08_24_core)

PDK: pdk_am57xx_1_0_13

BR: Per-Anders

  • Hi Per-Anders,

    Which McSPI4 DMA signal exactly you need to configure in DMA_CROSSBAR? There is no McSPI4 channel 4. We have McSPI4 channel 0 to 3.

    Refer to the below TRM section for more info regarding available McSPI DMA channels.

    24.4.3 McSPI Integration:

    MCSPI4_DREQ_TX0 - McSPI module 4 - transmit request channel 0
    MCSPI4_DREQ_RX0 - McSPI module 4 - receive request channel 0

    MCSPI4_DREQ_TX1 - McSPI module 4 - transmit request channel 1
    MCSPI4_DREQ_RX1 - McSPI module 4 - receive request channel 1

    MCSPI4_DREQ_TX2 - McSPI module 4 - transmit request channel 2
    MCSPI4_DREQ_RX2 - McSPI module 4 - receive request channel 2

    MCSPI4_DREQ_TX3 - McSPI module 4 - transmit request channel 3
    MCSPI4_DREQ_RX3 - McSPI module 4 - receive request channel 3


    Regards,
    Pavel
  • Hi, Sorry for the misunderstanding. 

    It's MCSPI3 channel 0. What We understand is that there is no default mapping in the SOC setup.

    In cslr_soc.h it says:

    /*
    * Cross Bar Mapped Please check before use
    */
    /* MCSPI3 CHA0 Receive Event */
    #define CSL_EDMA3_CHA0_MCSPI3_RX 23
    /* MCSPI3 CHA0 Transmit Event */
    #define CSL_EDMA3_CHA0_MCSPI3_TX 22

    So this is the question how to map them in a propper way. 

    /PAS

  • Per-Anders,

    From what I can see in AM572x TRM, MCSPI3 channel 0 is mapped by default. Refer to section "16.1.3.1 DMA Requests to the DMA_SYSTEM Controller". All DMA request from 0 to 126 are mapped by default, while 127 to 256 needs to be configured in the CROSSBAR.

    MCSPI3_DREQ_TX0 and MCSPI3_DREQ_RX0 are 14 (DMA_SYSTEM_DREQ_14) and 15 (DMA_SYSTEM_DREQ_15) and are mapped by default in below register:

    CTRL_CORE_DMA_SYSTEM_DREQ_14_15[7:0] DMA_SYSTEM_DREQ_14 = 0xF (15)

    CTRL_CORE_DMA_SYSTEM_DREQ_14_15[23:16] DMA_SYSTEM_DREQ_15 = 0x10 (16)

    You can check this CTRL_CORE_DMA_SYSTEM_DREQ_14_15 register. If you have the default/reset value there, then McSPI3 channel 0 events are mapped to DMA 14 and 15 events.


    If for example you need to use McSPI4 channel 3, there is no default mapping and you need to map by yourself.

    This is valid for SDMA, but we have the same for EDMA.

    Regards,
    Pavel
  • Hi,Yes you are correct but I think there is some misunderstanding about the numbering of the MCSPI devices. :-)

    Some places they are from MCSPI(1 to 4) and other (in the other places (0 - 3)

    In the cslr_soc.h the numbering is and I used that one, see below:

    /* MCSPIx Channelx */

    /* MCSPI0 CHA0 Receive Event */

    #define CSL_EDMA3_CHA0_MCSPI0_RX 35

    ---------------------

    /* MCSPI1 CHA0 Receive Event */

    #define CSL_EDMA3_CHA0_MCSPI1_RX 43

    -----------------------

    /* MCSPI2 CHA0 Receive Event */

    #define CSL_EDMA3_CHA0_MCSPI2_RX 15

     

    *

    * Cross Bar Mapped Please check before use

    */

    /* MCSPI3 CHA0 Receive Event */

    #define CSL_EDMA3_CHA0_MCSPI3_RX 23

    /* MCSPI3 CHA0 Transmit Event */

    #define CSL_EDMA3_CHA0_MCSPI3_TX 22

     

     

    As you mentioned McSPI3 CH0 is default mapped to 14/15 and this channel works perfectly, but if we use the numbering McSPI[1-4], it's

    McSPI4 channel 0 that We can't figure out how to remap. Sorry for making things confusing.

    Can you provide some hints, code how to do this remapping?

    BR

    Per-Amders

  • Per-Amders,

    McSPI4 (base addr 0x480BA000) (numbering 1-4), channel 0 is also mapped by default. All DMA request from 0 to 126 are mapped by default, and McSPI4 channel 0 are 69 and 70 for SDMA.

    MCSPI4_DREQ_TX0 and MCSPI4_DREQ_RX0 are 69 (DMA_SYSTEM_DREQ_69) and 70 (DMA_SYSTEM_DREQ_70) and are mapped by default in below registers:

    CTRL_CORE_DMA_SYSTEM_DREQ_68_69[23:16] DMA_SYSTEM_DREQ_69 = 0x46 (70)

    CTRL_CORE_DMA_SYSTEM_DREQ_70_71[7:0] DMA_SYSTEM_DREQ_70 = 0x47 (71)

    You can check these CTRL_CORE_DMA_SYSTEM_DREQ_68_69 and CTRL_CORE_DMA_SYSTEM_DREQ_70_71 registers. If you have the default/reset value there, then McSPI4 channel 0 events are mapped to SDMA 69 and 70 events.

    The default mapping is only for SDMA, not for EDMA, check TRM Table 24-294. McSPI Hardware Requests.

    Regards,
    Pavel