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Part Number: 66AK2H14
1. What's the difference between C66x XMC MPAX and MSMC MPAX in Keystone II devices?
2. If transferring data between DDR3A and L2 SRAM via EDMA in Keystone II, should MPAX setting be assigned with PrivID = 0?
3. Can MPAX translate any logic memory address, e.g. 0x0400_0000, in Keystone II devices?
The Extended Memory Controller (XMC) in C66x DSP CorePac serves as the L2 memory controller’s MDMA path to the MSMC. XMC has three additional responsibilities: Memory protection, Address extension, and Prefetch.
Memory protection and address extension (MPAX) are provided together in a unit called MPAX. With XMC’s MPAX feature, C66x CorePac supports systems with address widths up to 36 bits, despite only supporting 32-bit addresses internally. The memory protection step determines what types of accesses are permitted on various address ranges within C66x CorePac’s 32-bit address map. The address extension step projects those accesses onto a larger 36-bit address space.
Additionally, there are MPAX units in the chip level MSMC, which is external to the C66x CorePac. Both system slave interfaces, shared SRAM (SMS) and external memory (SMS), in MSMC feature an MPAX unit similar to the MPAX unit inside the C66x CorePac. The MSMC module MPAX supports an external memory addressing space of up to 32 GBytes addressable with a 36-bit address, even though the SoC addressing remains at 32-bits. Some KeyStone II devices (see device-specific data sheet) can support only up to 8 GBytes of external memory space.
The C66x CorePac uses its own MPAX units to extend 32-bit addresses to 36-bit addresses before presenting them to the MSMC module. The ARM CorePac can optionally use the MMU with LPAE (Large Physical Address Extension) to support 40 bit physical addressing. However the 4 MSBs of the physical address should be set to 0x0 in KeyStone II devices in the ARM MMU. The slave interfaces on the MSMC that receive addresses from all other masters in the system must extend the address inside the MSMC. These interfaces also provide support for memory protection for accesses from system masters to MSMC SRAM, external memory, and memory-mapped registers in the EMIF.
EDMA uses 32-bit address for the Parameter set: SRC and DST. For L2, global address need to be used. For DDR3A, the 36-bit address needs to be mapped to 32-bit address via MPAX.
The MPAX process is performed for a variable-sized segment of memory and is controlled with a register pair for each segment: MPAXH and MPAXL control registers.
• The MPAXH specifies the base address and size of the segment to match.
• The MPAXL specifies the replacement address and permissions for the segment.
Each MPAX unit provides eight control register pairs per Privilege ID (PrivID) of the system masters, which allows eight independent and potentially overlapping variable-size memory segments to be operated upon. Keystone II data sheet lists the Privilege ID (PrivID) values assigned for various system masters, the privilege level (supervisor vs. user), security level (secure vs. nonsecure), and access type (instruction read vs. data/DMA read or write) of each master.
No, accesses to the range 0x00000000-0x07FFFFFF are decoded by the CorePac itself, and are not presented to the MPAX unit of the XMC controller. Furthemore, accesses to the range 0x08000000-0x0BFFFFFF are considered accesses to memory mapped control registers. The MPAX unit does not modify these addresses, nor does it perform a segment-based protection check for accesses in this range, regardless of whether a segment overlaps this range.
Note DDR3A can only be translated to address above 0x8000:0000 for master like EDMA or PCIE. It will fail if translating DDR3A 0x8:0000:0000 to logical address lower than 0x8000:0000 via MPAX with EDMA master.
To address the most common mistakes on AK2H processors.
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