Hi all,
I don't understand something in a CCS project I wrote. In my test I only write data in DDR3. I did two tests: one using DDR3 cacheable and an other one using DDR3 non-cacheable (through MAR).
For this test, I don't use any OS, L2 is used as full SRAM (no cache) and L1D as full cache.
I expecting no data in cache for those two tests.
In this test, I wrote data in different memory block each time and each write will be 'miss' (no rewritting data), if I have a good understanding of the DSP cache and DDR3 memory controller documentations from 66AK2H14 related documentations:
L1D is read-allocate/writeback, in my case I don't do any reads (only write), I expecting no data in cache because in case of write 'miss' documentation says that data pass through Write buffer and go directly to external memory or L2 (in my case DDR3).
Yet, when I look into cache view under CCS, from exactly 262 142 Bytes written, the cache is used.
Why ?
Regards,
François