RTOS/PROCESSOR-SDK-AM437X: Ethernet PHY not detected

sayali pathak

Part Number: AM4379
Other Parts Discussed in Thread: TPS65218,

Tool/software: TI-RTOS

Hello,

We have Am437x board interfaced with kollmorgen drive through ethercat cable. we get following output on putty during power on board:

Trying to boot from MMC2

SPL: Please implement spl_start_uboot() for your board

SPL: Direct Linux boot not active!

reading u-boot.img

U-Boot 2016.05 (Mar 01 2017 - 14:44:57 +0800)

I2C: ready

DRAM: 512 MiB

PMIC: TPS65218

MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1

Card did not respond to voltage select!

** Bad device mmc 0 **

Using default environment

Net: <ethaddr> not set. Validating first E-fuse MAC

Could not get PHY for cpsw: addr 0

Could not get PHY for cpsw: addr 1

Could not get PHY for cpsw: addr 6

cpsw, usb_ether

Hit any key to stop autoboot: 0

Card did not respond to voltage select!

switch to partitions #0, OK

mmc1(part 0) is current device

switch to partitions #0, OK

mmc1(part 0) is current device

SD/MMC found on device 1

4527760 bytes read in 519 ms (8.3 MiB/s)

48868 bytes read in 16 ms (2.9 MiB/s)

Booting from mmc1 ...

Kernel image @ 0x82000000 [ 0x000000 - 0x451690 ]

## Flattened Device Tree blob at 88000000

Booting using the fdt blob at 0x88000000

Loading Device Tree to 8fff1000, end 8ffffee3 ... OK

Starting kernel ...

[ 0.000000] Booting Linux on physical CPU 0x0

[ 0.000000] Initializing cgroup subsys cpu

[ 0.000000] Initializing cgroup subsys cpuacct

[ 0.000000] Linux version 4.1.18 (sunny@myir-server1) (gcc version 5.4.0 (Buildroot 2017.02-git-00458-g3a0e257) ) #1 PREEMPT Wed Mar 1 14:42:44 CST 2017

[ 0.000000] CPU: ARMv7 Processor [412fc09a] revision 10 (ARMv7), cr=10c5387d

[ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache

[ 0.000000] Machine model: MYIR-TECH MYD_C437X_PRU Industrial Development Kit

[ 0.000000] cma: Reserved 24 MiB at 0x9e800000

[ 0.000000] Memory policy: Data cache writeback

[ 0.000000] CPU: All CPU(s) started in SVC mode.

[ 0.000000] AM437x ES1.2 (neon )

[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 129920

[ 0.000000] Kernel command line: console=ttyO0,115200n8 root=PARTUUID=00000000-02 rw rootfstype=ext4 rootwait

[ 0.000000] PID hash table entries: 2048 (order: 1, 8192 bytes)

[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)

[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)

[ 0.000000] Memory: 484792K/524288K available (6407K kernel code, 258K rwdata, 2392K rodata, 276K init, 234K bss, 14920K reserved, 24576K cma-reserved, 0K highmem)

[ 0.000000] Virtual kernel memory layout:

[ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB)

[ 0.000000] fixmap : 0xffc00000 - 0xfff00000 (3072 kB)

[ 0.000000] vmalloc : 0xe0800000 - 0xff000000 ( 488 MB)

[ 0.000000] lowmem : 0xc0000000 - 0xe0000000 ( 512 MB)

[ 0.000000] pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB)

[ 0.000000] modules : 0xbf000000 - 0xbfe00000 ( 14 MB)

[ 0.000000] .text : 0xc0008000 - 0xc08a005c (8801 kB)

[ 0.000000] .init : 0xc08a1000 - 0xc08e6000 ( 276 kB)

[ 0.000000] .data : 0xc08e6000 - 0xc0926bf0 ( 259 kB)

[ 0.000000] .bss : 0xc0929000 - 0xc0963bec ( 235 kB)

[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1

[ 0.000000] Preemptible hierarchical RCU implementation.

[ 0.000000] Additional per-CPU info printed with stalls.

[ 0.000000] NR_IRQS:16 nr_irqs:16 16

[ 0.000000] L2C: platform modifies aux control register: 0x0e030000 -> 0x3e430000

[ 0.000000] L2C: DT/platform modifies aux control register: 0x0e030000 -> 0x3e430000

[ 0.000000] L2C-310 enabling early BRESP for Cortex-A9

[ 0.000000] OMAP L2C310: ROM does not support power control setting

[ 0.000000] L2C-310 ID prefetch enabled, offset 1 lines

[ 0.000000] L2C-310 dynamic clock gating disabled, standby mode disabled

[ 0.000000] L2C-310 cache controller enabled, 16 ways, 256 kB

[ 0.000000] L2C-310: CACHE_ID 0x410000c9, AUX_CTRL 0x7e430000

[ 0.000000] OMAP clockevent source: timer2 at 24000000 Hz

[ 0.000013] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns

[ 0.000035] clocksource timer1: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns

[ 0.000047] OMAP clocksource: timer1 at 24000000 Hz

[ 0.001207] Console: colour dummy device 80x30

[ 0.001244] Calibrating delay loop... 1196.85 BogoMIPS (lpj=5984256)

[ 0.090229] pid_max: default: 32768 minimum: 301

[ 0.090341] Security Framework initialized

[ 0.090392] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)

[ 0.090406] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)

[ 0.091176] Initializing cgroup subsys blkio

[ 0.091203] Initializing cgroup subsys memory

[ 0.091256] Initializing cgroup subsys devices

[ 0.091276] Initializing cgroup subsys freezer

[ 0.091293] Initializing cgroup subsys perf_event

[ 0.091323] CPU: Testing write buffer coherency: ok

[ 0.091709] Setting up static identity map for 0x80008200 - 0x80008270

[ 0.093659] devtmpfs: initialized

[ 0.108204] VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4

[ 0.190569] clocksource jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns

[ 0.192676] pinctrl core: initialized pinctrl subsystem

[ 0.194044] NET: Registered protocol family 16

[ 0.195861] DMA: preallocated 256 KiB pool for atomic coherent allocations

[ 0.220220] cpuidle: using governor ladder

[ 0.250209] cpuidle: using governor menu

[ 0.252583] omap_l3_noc 44000000.ocp: L3 debug error: target 8 mod:0 (unclearable)

[ 0.252659] omap_l3_noc 44000000.ocp: L3 application error: target 8 mod:0 (unclearable)

[ 0.258158] OMAP GPIO hardware version 0.1

[ 0.259565] omap_gpio 481ae000.gpio: could not find pctldev for node /ocp/l4_wkup@44c00000/scm@210000/pinmux@800/gpio3_pins_default, deferring probe

[ 0.259932] omap_gpio 48320000.gpio: could not find pctldev for node /ocp/l4_wkup@44c00000/scm@210000/pinmux@800/gpio4_pins_default, deferring probe

[ 0.267859] No ATAGs?

[ 0.267900] hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.

[ 0.267913] hw-breakpoint: maximum watchpoint size is 4 bytes.

[ 0.311080] edma 49000000.edma: TI EDMA DMA engine driver

[ 0.315655] vgaarb: loaded

[ 0.316244] SCSI subsystem initialized

[ 0.316935] omap_i2c 44e0b000.i2c: could not find pctldev for node /ocp/l4_wkup@44c00000/scm@210000/pinmux@800/i2c0_pins_default, deferring probe

[ 0.316995] omap_i2c 4819c000.i2c: could not find pctldev for node /ocp/l4_wkup@44c00000/scm@210000/pinmux@800/i2c2_pins_default, deferring probe

[ 0.317140] media: Linux media interface: v0.10

[ 0.317219] Linux video capture interface: v2.00

[ 0.317297] pps_core: LinuxPPS API ver. 1 registered

[ 0.317347] PTP clock support registered

[ 0.318242] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400

[ 0.318541] Advanced Linux Sound Architecture Driver Initialized.

[ 0.319382] Switched to clocksource timer1

[ 0.331329] NET: Registered protocol family 2

[ 0.332254] TCP established hash table entries: 4096 (order: 2, 16384 bytes)

[ 0.332321] TCP bind hash table entries: 4096 (order: 2, 16384 bytes)

[ 0.332387] TCP: Hash tables configured (established 4096 bind 4096)

[ 0.332495] UDP hash table entries: 256 (order: 0, 4096 bytes)

[ 0.332518] UDP-Lite hash table entries: 256 (order: 0, 4096 bytes)

[ 0.332706] NET: Registered protocol family 1

[ 0.333095] RPC: Registered named UNIX socket transport module.

[ 0.333111] RPC: Registered udp transport module.

[ 0.333119] RPC: Registered tcp transport module.

[ 0.333127] RPC: Registered tcp NFSv4.1 backchannel transport module.

[ 0.335713] futex hash table entries: 256 (order: -1, 3072 bytes)

[ 0.335815] audit: initializing netlink subsys (disabled)

[ 0.335877] audit: type=2000 audit(0.310:1): initialized

[ 0.343304] VFS: Disk quotas dquot_6.6.0

[ 0.343537] VFS: Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)

[ 0.345842] NFS: Registering the id_resolver key type

[ 0.345913] Key type id_resolver registered

[ 0.345923] Key type id_legacy registered

[ 0.348021] NET: Registered protocol family 38

[ 0.348097] io scheduler noop registered

[ 0.348116] io scheduler deadline registered

[ 0.348189] io scheduler cfq registered (default)

[ 0.350825] pinctrl-single 44e10800.pinmux: 199 pins at pa f9e10800 size 796

[ 0.353543] backlight supply power not found, using dummy regulator

[ 0.355604] wkup_m3_ipc 44e11324.wkup_m3_ipc: could not get rproc handle

[ 0.356949] Serial: 8250/16550 driver, 10 ports, IRQ sharing enabled

[ 0.360976] omap_uart 44e09000.serial: no wakeirq for uart0

[ 0.361023] omap_uart 44e09000.serial: No clock speed specified: using default: 48000000

[ 0.361206] 44e09000.serial: ttyO0 at MMIO 0x44e09000 (irq = 30, base_baud = 3000000) is a OMAP UART0

[ 1.113815] console [ttyO0] enabled

[ 1.118121] omap_uart 481a6000.serial: no wakeirq for uart3

[ 1.124124] omap_uart 481a6000.serial: No clock speed specified: using default: 48000000

[ 1.132893] 481a6000.serial: ttyO3 at MMIO 0x481a6000 (irq = 31, base_baud = 3000000) is a OMAP UART3

[ 1.143242] omap_uart 481aa000.serial: no wakeirq for uart5

[ 1.149594] [drm] Initialized drm 1.1.0 20060810

[ 1.167389] brd: module loaded

[ 1.176675] loop: module loaded

[ 1.181257] mtdoops: mtd device (mtddev=name/number) must be supplied

[ 1.249446] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6

[ 1.255913] davinci_mdio 4a101000.mdio: detected phy mask ffffffef

[ 1.263473] libphy: 4a101000.mdio: probed

[ 1.267723] davinci_mdio 4a101000.mdio: phy[4]: device 4a101000.mdio:04, driver Atheros 8035 ethernet

[ 1.278328] cpsw 4a100000.ethernet: Missing slave[1] phy_id property

[ 1.285174] cpsw 4a100000.ethernet: Detected MACID = 60:64:05:05:65:5b

[ 1.294146] mousedev: PS/2 mouse device common for all mice

[ 1.300264] i2c /dev entries driver

[ 1.306066] omap_hsmmc 48060000.mmc: Got CD GPIO

[ 1.369814] ledtrig-cpu: registered to indicate activity on CPUs

[ 1.376870] remoteproc0: wkup_m3 is available

[ 1.381675] remoteproc0: Note: remoteproc is still under development and considered experimental.

[ 1.391204] remoteproc0: THE BINARY FORMAT IS NOT YET FINALIZED, and backward compatibility isn't yet guaranteed.

[ 1.404586] oprofile: no performance counters

[ 1.409337] oprofile: using timer interrupt.

[ 1.414341] Initializing XFRM netlink socket

[ 1.418913] NET: Registered protocol family 17

[ 1.423746] NET: Registered protocol family 15

[ 1.428567] Key type dns_resolver registered

[ 1.433407] omap_voltage_late_init: Voltage driver support not added

[ 1.440606] cpu cpu0: of_pm_voltdm_notifier_register: Failed to get cpu0 regulator/voltdm: -517

[ 1.449912] cpu cpu0: cpu0 clock notifier not ready, retry

[ 1.456130] ThumbEE CPU extension supported.

[ 1.460745] Registering SWP/SWPB emulation handler

[ 1.468645] GPIO line 104 (EMMC_RST) hogged as output/high

[ 1.475426] GPIO line 147 (SelPRUorLCDEN) hogged as output/low

[ 1.481718] GPIO line 149 (SelPRUorLCDSEL) hogged as output/low

[ 1.509620] rtc-rx8025t 0-0032: power-on reset was detected, you may have to readjust the clock

[ 1.518839] rtc-rx8025t 0-0032: a power voltage drop was detected, you may have to readjust the clock

[ 1.528740] rtc-rx8025t 0-0032: bad conditions detected, resetting date

[ 1.536638] rtc-rx8025t 0-0032: rtc core: registered rx8025t as rtc0

[ 1.554776] omap_i2c 44e0b000.i2c: bus 0 rev0.12 at 400 kHz

[ 1.561980] omap_i2c 4819c000.i2c: bus 2 rev0.12 at 100 kHz

[ 1.568995] omap_uart 481aa000.serial: no wakeirq for uart5

[ 1.574994] remoteproc0: powering up wkup_m3

[ 1.579720] omap_uart 481aa000.serial: No clock speed specified: using default: 48000000

[ 1.588438] remoteproc0: Booting fw image am335x-pm-firmware.elf, size 219803

[ 1.596936] remoteproc0: remote processor wkup_m3 is now up

[ 1.602993] wkup_m3_ipc 44e11324.wkup_m3_ipc: CM3 Firmware Version = 0x191

[ 1.610346] 481aa000.serial: ttyO5 at MMIO 0x481aa000 (irq = 32, base_baud = 3000000) is a OMAP UART5

[ 1.622174] omap_hsmmc 48060000.mmc: Got CD GPIO

[ 1.699813] cpu cpu0: of_pm_voltdm_notifier_register: Fail calculating voltage latency[1100000<->1325000]:-22

[ 1.710701] cpu cpu0: of_pm_voltdm_notifier_register: Fail calculating voltage latency[1100000<->1325000]:-22

[ 1.723704] rtc-rx8025t 0-0032: setting system clock to 1970-01-01 00:00:00 UTC (0)

[ 1.741054] ALSA device list:

[ 1.744195] No soundcards found.

[ 1.748307] Waiting for root device PARTUUID=00000000-02...

[ 1.773078] mmc1: MAN_BKOPS_EN bit is not set

[ 1.780856] mmc1: new high speed MMC card at address 0001

[ 1.787034] mmcblk0: mmc1:0001 Q2J54A 3.59 GiB

[ 1.792012] mmcblk0boot0: mmc1:0001 Q2J54A partition 1 16.0 MiB

[ 1.798376] mmcblk0boot1: mmc1:0001 Q2J54A partition 2 16.0 MiB

[ 1.805859] mmcblk0: p1 p2

[ 1.873158] EXT4-fs (mmcblk0p2): mounted filesystem with ordered data mode. Opts: (null)

[ 1.881830] VFS: Mounted root (ext4 filesystem) on device 179:2.

[ 1.890730] devtmpfs: mounted

[ 1.894345] Freeing unused kernel memory: 276K (c08a1000 - c08e6000)

INIT: version 2.88 booting

[ 2.068797] EXT4-fs (mmcblk0p2): re-mounted. Opts: errors=remount-ro,data=ordered

INIT: Entering runlevel: 3

Starting logging: OK

modprobe: module mmc_core not found in modules.dep

modprobe: module mmc_block not found in modules.dep

modprobe: module omap_hsmmc not found in modules.dep

Populating /dev using udev: [ 2.942005] ov2659 0-0030: Sensor detection failed (3030, 0)

[ 3.248437] PM: bootloader does not support rtc-only!

[ 3.566789] prueth 54400000.pruss:pruss1_eth: port 1: using random MAC addr: ea:83:66:31:90:ab

[ 3.670730] prueth 54400000.pruss:pruss1_eth: port 2: using random MAC addr: 26:d1:41:cb:e6:c6

done

Initializing random number generator... done.

Starting network: [ 4.730356] libphy: PHY not found

[ 4.733936] net eth0: phy not found on slave 1

udhcpc: started, v1.25.1

udhcpc: sending discover

udhcpc: no lease, failing

FAIL

Starting sshd: OK

Initializing SGX graphics driver PVR:(Error): OpenServices: Cannot open device driver /dev/omapdrm_pvr. [140, /pvr_bridge_u.c]

PVR:(Error): PVRSRVInitSrvConnect: PVRSRVConnect failed [2572, /bridged_pvr_glue.c]

PVR:(Error): SrvInit: PVRSRVInitSrvConnect failed (4) [37, /srvinit.c]

PVR:(Error): main: SrvInit failed (4) [49, /pvrsrvinit.c]

FAIL

please suggest what to be done.

over 4 years ago

0 Biser Gatchev-XID over 4 years ago

TI__Guru**** 393215 points

You are asking about RTOS and EtherCAT, yet you have posted a Linux boot log. Please explain clearly and in detail what you are trying to do, what software are you using, which version, etc... full details of your use case.

0 sayali pathak over 4 years ago

Expert 1245 points

Part Number: AM4379

Tool/software: TI-RTOS

Hi,

I try to use Am437x board for ethercat communication between PC and drive. I have taken EcMAsterDemo code from acountis site. However, I encountered the problem "No source available for "0x35aaa" when entering the CCS debug mode. Why such time of errors occurred?? What does this error mean?? How to resolve it??

0 sayali pathak over 4 years ago in reply to Biser Gatchev-XID

Expert 1245 points

Hi,

I just want to mplement ethercat communication between kollmorgen drive and PC. I have taken EC masterdemo code attached below for your reference. when i run the code i got message on putty.

2480.main.c

/*-----------------------------------------------------------------------------
 * main.c
 * Copyright                acontis technologies GmbH, Weingarten, Germany
 * Description              EtherCAT Master demo application
 *---------------------------------------------------------------------------*/

#include <xdc/std.h>
#include <xdc/runtime/Error.h>
#include <xdc/runtime/System.h>
#include <ti/sysbios/BIOS.h>
#include <ti/sysbios/knl/Task.h>
#include <ti/sysbios/family/arm/a8/Mmu.h>
#include <ti/sysbios/timers/dmtimer/Timer.h>
#include <ti/sysbios/hal/Cache.h>
/* EcMaster version */
#include <EcVersion.h>
/* includes from demo  */
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
/* EMAC Driver Header File. */
#include <ti/drv/emac/emac_drv.h>
#include <ti/drv/emac/src/v4/emac_drv_v4.h>
#include <ti/drv/emac/soc/emac_soc_v4.h>

#include <ti/board/board.h>
#include <ti/drv/gpio/GPIO.h>
#include <ti/drv/gpio/soc/GPIO_v1.h>

#include <ti/starterware/include/hw/hw_control_am43xx.h>
#include <ti/starterware/include/hw/am437x.h>
#include <ti/starterware/include/ethernet.h>

#include <ti/sysbios/timers/dmtimer/Timer.h>

/* UART Header files */
#include <ti/drv/uart/UART.h>
#include <ti/drv/uart/UART_stdio.h>
/* Clock source macros for enabling specified DMTIMER */
#define CM_PER_TIMER3_CLKCTRL       (0x44DF8800 + 0x538)        // PRCM_CM_PER_TIMER3_CLKCTRL
#define CM_DPLL_CLKSEL_TIMER3_CLK   (0x44DF4200 + 0x8)

#define DMTIMER3                    3
#define TIMER_ID                    DMTIMER3

void TimerEmptyISR();


/********************************************************************************/
/** \brief Puts string to the UART and replace "\n" to "\n\r"
*
* \return N/A
*/
static int UARTPutStringWithCR(char* pStr, int maxLength)
{
    int symCount = 0;
    char* pCurrent = pStr;

    while (*pCurrent != 0)
    {
        Char curChar = *pCurrent;
        if ( '\n' == curChar )
        {
        	UART_putc('\n');
        	UART_putc('\r');
        }
        else
        	UART_putc(curChar);

        symCount++;

        pCurrent++;
    }

    return symCount;
}

/********************************************************************************/
/** \brief Puts string to the UART
*
* \return printed symbols count
*/
#define MAX_TRACE_MSGLEN 255
int UARTVprintf(const char *szFormat, va_list vaArgs)
{
    char achMsg[MAX_TRACE_MSGLEN];
    vsnprintf(achMsg, MAX_TRACE_MSGLEN, szFormat, vaArgs);

    return UARTPutStringWithCR(achMsg, MAX_TRACE_MSGLEN);
}
/* Enable the below macro to have prints on the IO Console */
//#define IO_CONSOLE

#ifndef IO_CONSOLE
#define NIMU_log                UART_printf
#else
#define NIMU_log                printf
#endif
/* ========================================================================== */
/*                             Macros                                         */
/* ========================================================================== */

#define MAX_TABLE_ENTRIES   3

#define GPIO_USER0_LED_PIN_NUM    (0x0B)
#define GPIO_USER0_LED_PORT_NUM   (0x05)
#define GPIO_USER1_LED_PIN_NUM    (0x0A)
#define GPIO_USER1_LED_PORT_NUM   (0x05)

#define SYS_MMU_BUFFERABLE      1
#define SYS_MMU_CACHEABLE       2
#define SYS_MMU_SHAREABLE       4
#define SYS_MMU_NO_EXECUTE      8


/* ========================================================================== */
/*                            Global Variables                                */
/* ========================================================================== */

/**Task handle for EIP*/
Task_Handle main_task;
uint8_t board_type = 0;

//NIMU_DEVICE_TABLE_ENTRY NIMUDeviceTable[MAX_TABLE_ENTRIES];
void TaskFxn(UArg a0, UArg a1);
/* GPIO Driver board specific pin configuration structure */
GPIO_PinConfig gpioPinConfigs[] = {
									/* Input pin with interrupt enabled */
									GPIO_DEVICE_CONFIG(( GPIO_USER0_LED_PORT_NUM + 1 ), GPIO_USER0_LED_PIN_NUM) |
									GPIO_CFG_IN_INT_RISING | GPIO_CFG_INPUT,

									/* Output pin */
									GPIO_DEVICE_CONFIG( (GPIO_USER0_LED_PORT_NUM + 1), GPIO_USER0_LED_PIN_NUM) |
									GPIO_CFG_OUTPUT
								  };

/* GPIO Driver call back functions */
GPIO_CallbackFxn gpioCallbackFunctions[] = {
										      NULL,
											  NULL
										   };

/* GPIO Driver configuration structure */
GPIO_v1_Config GPIO_v1_config = {
								  gpioPinConfigs,
								  gpioCallbackFunctions,
								  sizeof(gpioPinConfigs) / sizeof(GPIO_PinConfig),
							      sizeof(gpioCallbackFunctions) / sizeof(GPIO_CallbackFxn),
							      0,
								};

/* ========================================================================== */
/*                            Local Variables                                 */
/* ========================================================================== */

typedef struct _sys_mmu_entry
{

    void* address;
    /**< Address to be entered in MMU table. */
    unsigned int attributes;
    /**< Attributes of the memory. */
}SYS_MMU_ENTRY;


SYS_MMU_ENTRY applMmuEntries[] = {
    {(void*)0x30000000,SYS_MMU_CACHEABLE},  //QSPI CS0 Maddr1space - Cacheable
    {(void*)0x30100000,SYS_MMU_CACHEABLE},  //QSPI CS0 Maddr1space - Cacheable
    {(void*)0x30200000,SYS_MMU_CACHEABLE},  //QSPI CS0 Maddr1space - Cacheable
    {(void*)0x30300000,SYS_MMU_CACHEABLE},  //QSPI CS0 Maddr1space - Cacheable
    {(void*)0x40300000,0},  //OCMCRAM  - Cacheable
    {(void*)0x44D00000, SYS_MMU_BUFFERABLE},  //PRCM - Non bufferable| Non Cacheable
    {(void*)0x44E00000, SYS_MMU_BUFFERABLE},  //Clock Module, PRM, GPIO0, UART0, I2C0, - Non bufferable| Non Cacheable
    {(void*)0x47900000,SYS_MMU_BUFFERABLE},  //QSPI MMR Maddr0space
    {(void*)0x48000000, SYS_MMU_BUFFERABLE},  //UART1,UART2,I2C1,McSPI0,McASP0 CFG,McASP1 CFG,DMTIMER,GPIO1 -Non bufferable| Non Cacheable
    {(void*)0x48100000,0},  //I2C2,McSPI1,UART3,UART4,UART5, GPIO2,GPIO3,MMC1 - Non bufferable| Non Cacheable
    {(void*)0x48200000, SYS_MMU_BUFFERABLE},  //
    {(void*)0x48300000, SYS_MMU_BUFFERABLE},  //PWM - Non bufferable| Non Cacheable
    {(void*)0x49000000, SYS_MMU_BUFFERABLE},   //EDMA3CC - Non bufferable| Non Cacheable
    {(void*)0x4A000000, SYS_MMU_BUFFERABLE},  //L4 FAST CFG- Non bufferable| Non Cacheable
    {(void*)0x4A100000, SYS_MMU_BUFFERABLE},  //CPSW - Non bufferable| Non Cacheable
    {(void*)0x54400000, SYS_MMU_BUFFERABLE},  //PRU-ICSS0/1 -Bufferable| Non Cacheable | Shareable
    {(void*)0x80000000,SYS_MMU_CACHEABLE},  //QSPI CS0 Maddr1space - Non bufferable| Non Cacheable
    {(void*)0xFFFFFFFF,0xFFFFFFFF}
};

int SDKMMUInit(SYS_MMU_ENTRY mmuEntries[])
{
    unsigned short itr = 0;
    Mmu_FirstLevelDescAttrs attrs;

    if(NULL == mmuEntries)
        return -1;

    Mmu_disable();

    Mmu_initDescAttrs(&attrs);

    attrs.type = Mmu_FirstLevelDesc_SECTION;
    attrs.domain = 0;
    attrs.imp = 1;
    attrs.accPerm = 3;


    for(itr = 0 ; mmuEntries[itr].address != (void*)0xFFFFFFFF ; itr++)
    {
        attrs.bufferable = ((mmuEntries[itr].attributes) & SYS_MMU_BUFFERABLE) && 1 ;
        attrs.cacheable  = ((mmuEntries[itr].attributes) & SYS_MMU_CACHEABLE) && 1;
        if (!attrs.bufferable && !attrs.cacheable)
            attrs.tex = 0; //tex is initialized to 1 and need this to force strongly ordered
        attrs.shareable  = ((mmuEntries[itr].attributes) & SYS_MMU_SHAREABLE) && 1;
        attrs.noexecute  = ((mmuEntries[itr].attributes) & SYS_MMU_NO_EXECUTE) && 1;
        Mmu_setFirstLevelDesc((Ptr)(mmuEntries[itr].address), (Ptr)(mmuEntries[itr].address) , &attrs);  // PWM
    }
    Mmu_enable();
    return 0;
}

void CpswPortMacModeSelect(uint32_t portNum, uint32_t macMode)
{
    uint32_t regVal = 0U;

    regVal = HW_RD_REG32(SOC_CONTROL_MODULE_REG + CTRL_GMII_SEL);

    switch(macMode)
    {
        case ETHERNET_MAC_TYPE_MII:
        case ETHERNET_MAC_TYPE_GMII:
            if(1U == portNum)
            {
                HW_SET_FIELD(regVal, CTRL_GMII_SEL_GMII1, 0U);
                HW_SET_FIELD(regVal, CTRL_GMII_SEL_RGMII1_IDMODE, 0U);
                HW_SET_FIELD(regVal, CTRL_GMII_SEL_RMII1_IO_CLK_EN, 0U);
            }
            else if(2U == portNum)
            {
                HW_SET_FIELD(regVal, CTRL_GMII_SEL_GMII2, 0U);
                HW_SET_FIELD(regVal, CTRL_GMII_SEL_RGMII2_IDMODE, 0U);
                HW_SET_FIELD(regVal, CTRL_GMII_SEL_RMII2_IO_CLK_EN, 0U);
            }
            else
            {
                /* This error does not happen because of check done already */
            }
            break;

        case ETHERNET_MAC_TYPE_RMII: /* RMII */
            if(1U == portNum)
            {
                HW_SET_FIELD(regVal, CTRL_GMII_SEL_GMII1, 1U);
                HW_SET_FIELD(regVal, CTRL_GMII_SEL_RGMII1_IDMODE, 0U);
                HW_SET_FIELD(regVal, CTRL_GMII_SEL_RMII1_IO_CLK_EN, 0U);
            }
            else if(2U == portNum)
            {
                HW_SET_FIELD(regVal, CTRL_GMII_SEL_GMII2, 1U);
                HW_SET_FIELD(regVal, CTRL_GMII_SEL_RGMII2_IDMODE, 0U);
                HW_SET_FIELD(regVal, CTRL_GMII_SEL_RMII2_IO_CLK_EN, 0U);
            }
            else
            {
                /* This error does not happen because of check done already */
            }
            break;

        case ETHERNET_MAC_TYPE_RGMII: /* RGMII */
            if(1U == portNum)
            {
                HW_SET_FIELD(regVal, CTRL_GMII_SEL_GMII1, 2U);
                HW_SET_FIELD(regVal, CTRL_GMII_SEL_RGMII1_IDMODE, 0U);
                HW_SET_FIELD(regVal, CTRL_GMII_SEL_RMII1_IO_CLK_EN, 0U);
            }
            else if(2U == portNum)
            {
                HW_SET_FIELD(regVal, CTRL_GMII_SEL_GMII2, 2U);
                HW_SET_FIELD(regVal, CTRL_GMII_SEL_RGMII2_IDMODE, 0U);
                HW_SET_FIELD(regVal, CTRL_GMII_SEL_RMII2_IO_CLK_EN, 0U);
            }
            else
            {
                /* This error does not happen because of check done already */
            }
            break;

         default:
         break;
    }

    HW_WR_REG32((SOC_CONTROL_MODULE_REG + CTRL_GMII_SEL), regVal);
}


/**
 *  \name main
 *  \brief Main Function
 *  \param none
 *  \return none
 *
 */
int main(void)
{
    /* Call board init functions */
	Error_Block eb;
    Board_initCfg boardCfg;
    Task_Params taskParams;

    SDKMMUInit(applMmuEntries);

    boardCfg = BOARD_INIT_PINMUX_CONFIG | BOARD_INIT_MODULE_CLOCK | BOARD_INIT_UART_STDIO;
	Error_init(&eb);
    Board_init(boardCfg);

   /* Chip configuration MII/RMII selection */
    CpswPortMacModeSelect(1, ETHERNET_MAC_TYPE_RGMII);
    CpswPortMacModeSelect(2, ETHERNET_MAC_TYPE_RGMII);

	Task_Params_init(&taskParams);
	taskParams.priority = 1;
	taskParams.stackSize = 0x1400;
    taskParams.instance->name = "MainTask";
    main_task = Task_create (TaskFxn, &taskParams, &eb);

	BIOS_start();
    return(0);
}


/** \brief Auxiliary clock timer instance.
 *
 * Used inside EcMaster code for auxiliary clock.
 * If instance is NULL, than standard clock is used (not precise).
*/
Timer_Handle g_auxClocksTimerHandle = 0;

/*****************************************************************************/
/** \brief Initializes timer instance which is used from auxiliary clock.
*/
void InitAuxClockTimer()
{
   Error_Block     eb;
   Timer_Params    auxTimerParams;

   // clock source to CLK_M_OSC: 0x1   - high frequency input clock
   //                 CLK_32KHz: 0x2
   //                 TCLKIN   : 0x0   - external clock pin - not used.
   *(unsigned int*)CM_DPLL_CLKSEL_TIMER3_CLK = 0x1;

   /* enable the TIMER */
   *(unsigned int*)CM_PER_TIMER3_CLKCTRL = 0x2;

   Error_init(&eb);
   Timer_Params_init(&auxTimerParams);

   auxTimerParams.period = 2400;  // default extFreq.lo=24000000
   auxTimerParams.periodType = Timer_PeriodType_COUNTS;
   auxTimerParams.arg = 1;

   g_auxClocksTimerHandle = Timer_create(TIMER_ID, TimerEmptyISR,
                                   &auxTimerParams, &eb);
   if (g_auxClocksTimerHandle == NULL) {
       System_abort("Aux Timer create failed");
   }
}

/*****************************************************************************/
/** \brief Timer ISR which do nothing.
*/
void TimerEmptyISR()
{
}

/*****************************************************************************/
/** \brief Prototype of main task defined in another file.
*
*/
extern int EcMasterDemo(void);


/**
 *  \name TaskFxn
 *  \brief Task which do EIP initialization
 *  \param a0
 *  \param a1
 *  \return none
 *
 */
void TaskFxn(UArg a0, UArg a1)
{
	NIMU_log("\n\rSYS/BIOS EcMasterDemo CPSW Sample application\n\r");
	
    InitAuxClockTimer();
	/* Workarround call to cache function should exist in executable becuase linker does not want to add it */
    Cache_wbInv(&main_task, 1, Cache_Type_ALL, TRUE);

    EcMasterDemo();
}

0 Paula Carrillo over 4 years ago in reply to sayali pathak

TI__Mastermind 32730 points

Hi Sayali, I think you are trying EC-Master on Linux PSDK, and on TI-RTOS PSDK. May I suggest to keep debugging on TI-RTOS (E2E) first?. I don't think your issue is related with the OS version. I believe, or MasterENI.c file is somehow not correct, or your slave is not working properly (have you done any sanity check in this front?) or AM4379 IDK CPSW port is broken, or the ETH cable is broken..

Do you have another slave you can try? maybe something simple? and OI slave? or if you have another TI Sitara platfrom (list of supported TI platforms/EVMs here) we can quickly download prebuild PRU-ICSS EtherCAT slave, to convert Sitara's EVM in an EtherCAT slave.

thank you,

Paula

0 sayali pathak over 4 years ago in reply to Paula Carrillo

Expert 1245 points

Hi,

I tried connecting slave to EC engineer tool software to convert ESI to ENI file. The slave connected successfully on that software using same ethernet cable. So,there is no fault in cable and ENI file is also correct.

0 Paula Carrillo over 4 years ago in reply to sayali pathak

TI__Mastermind 32730 points

ah OK, just to confirm, you are using AM4379 IDK J4 (Gb Ethernet) connector right?

thank you,

Paula

0 sayali pathak over 4 years ago in reply to Paula Carrillo

Expert 1245 points

Hi,

No i am using PRU Ethernet 0 on am4379 board.

0 Paula Carrillo over 4 years ago in reply to sayali pathak

TI__Mastermind 32730 points

Hi Sayali, that is the mistake. We have EC-Master for PRU-ICSS EMAC and CPSW for AM335x and AM572x platforms. For AM437x we only have developed EC-Master for CPSW interface. Please try connecting to J4 and let us know

Thank you,

Paula

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RTOS/PROCESSOR-SDK-AM437X: Ethernet PHY not detected