Keystone2: reset Physical Count(CNTPCT in C14) reg in CP15 registers

Michael Lawnick

Hi,

this is Michael Lawnick from Nokia.

My colleague opened a question in <https://e2e.ti.com/support/processors/f/791/t/804481>

The answer by TI seemed not to be related to the problem:
We search for a method to reset CNTPCT without the need to do a power cycle. Is there a method to achieve this by software?

The underlying story: we need to monitor boot time. Our system is already delivered to customer and primary bootloader in a write protected flash device. So monitoring must base on an by-default enabled counter which either starts a zero after reset or can be set to zero before reset.

The only K2-SoC timer which is enabled by default seems to be CNTPCT.

over 4 years ago

0 Yordan Kovachev over 4 years ago

TI__Guru**** 161600 points

Hi,

This has been locked, because no feedback was provided for about a month.

Best Regards,
Yordan

0 Michael Lawnick over 4 years ago in reply to Yordan Kovachev

Intellectual 470 points

A lock hint to a related question doesn't really make sense :-(

0 Michael Lawnick over 4 years ago in reply to Michael Lawnick

Intellectual 470 points

Now I got the problem why you answered that orig message is locked: my original post was cut on saving to forum - restored to intended full content.

Michael

0 Yordan Kovachev over 4 years ago in reply to Michael Lawnick

TI__Guru**** 161600 points

Hi Michael,

Yes, I was not seeing your question.

Okay, I am not that familiar with the arm cortex integration in the Keystone devices. Let me consult with the design team.

Best Regards,
Yordan

0 Rahul Prabhu over 4 years ago in reply to Yordan Kovachev

TI__Guru** 114410 points

Michael,

From the ARM reference manual, it appears that the architecture does not contain anything to allow setting the value backwards. It has statements to say time cannot go backwards, and it starts at zero. Architecture reference manual section “The Generic Timer” which is B8 in v7 reference manual has the most that we could find on this module. Programmers guide does not state anything other than “incrementing”.

Scanning for OS level code on CNTPCT I can only see reading the counter. TI A15 CSL code also doesn`t provide any mechanism to reset or access this counter so it looks this was not a use case that we have supported in the past.

https://arm-software.github.io/CMSIS_5/Core_A/html/group__CMSIS__CNTPCT.html

In Summary: to me it looks like read is the only operation allowed, architecture guarantees it will never go backwards (a reset would have time go backwards for observers). I would check on the ARM forums for confirmation of this understanding.

Regards,

Rahul

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Keystone2: reset Physical Count(CNTPCT in C14) reg in CP15 registers