AM3352: DDR EDMA test fails

Prodigy 230 points

Replies: 17

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Part Number: AM3352

Dear

I am apply the tuning the DDR3 Timings for a new design based on the http://processors.wiki.ti.com/index.php/Sitara_Linux_Training:_Tuning_the_DDR3_Timings_on_BeagleBoneBlack wiki.

All works fine up to running the Scripts->AM335x DDR Tests->EDMA. here I get error.

Could anybody give me some tip to help find root cause?

As attachment the  EDMA test log and my Gel file.

Regards

Sébastienam3352 303MHz - with new CCS value board 12.gelam3352 400MHz - with new CCS value board 12.geledma_log.txt

17 Replies

  • There is most likely an issue with the timing or the leveling values.  

    Please run the following DSS script:  git.ti.com/sitara-dss-files/am335x-dss-files/blobs/master/am335x-ddr-analysis.dss

    Instructions for running the script can be found here:  git.ti.com/sitara-dss-files/am335x-dss-files/blobs/master/README

    Also, provide your DDR3 part number and your Ratio Seed spreadsheet

    Regards,

    James

  • In reply to JJD:

    Dear James,

    As attachment the AM335x_DDR_register_calc_tool.xls and the AM335x_DDR_register_calc_tool.xls

    There are two file for each because my system must be able to run RR3 at 303MHz (minimal speed) or 400MHz (max speed)

    My memory PN is IS43TR16640B-15GBLI from ISSI.

    Sébastien

    AM335x_DDR_register_calc_tool_ 400MHz.xls

    AM335x_DDR_register_calc_tool_303MHz.xls

    RatioSeed_AM335x_boards 400MHz.xls

    RatioSeed_AM335x_boards 303MHz.xls

  • In reply to Seb O:

    There were several parameters that were input incorrectly into the spreadsheets.  Also, I would like to try with INVERT_CLKOUT=1

    Can you try with these changes to the GEL for 400MHz:

    //*******************************************************************
    //DDR3 PHY parameters
    //*******************************************************************

    #define CMD_PHY_CTRL_SLAVE_RATIO 0x00000100
    #define CMD_PHY_INVERT_CLKOUT 0x00000001

    #define DATA_PHY_RD_DQS_SLAVE_RATIO 0x00000040
    #define DATA_PHY_FIFO_WE_SLAVE_RATIO 0x000000F6
    #define DATA_PHY_WR_DQS_SLAVE_RATIO 0x00000083
    #define DATA_PHY_WR_DATA_SLAVE_RATIO 0x000000C3

    #define DDR_IOCTRL_VALUE 0x0000018B

    //******************************************************************
    //EMIF parameters
    //******************************************************************
    #define ALLOPP_DDR3_READ_LATENCY 8
    #define ALLOPP_DDR3_SDRAM_TIMING1 0x088AE4E3
    #define ALLOPP_DDR3_SDRAM_TIMING2 0x262F7FDA
    #define ALLOPP_DDR3_SDRAM_TIMING3 0x50FFE2BF

    #define ALLOPP_DDR3_SDRAM_CONFIG 0x61A05232
    #define ALLOPP_DDR3_REF_CTRL 0x00000C30
    #define ALLOPP_DDR3_ZQ_CONFIG 0x50077D33

     

    And these changes to the GEL for 303MHz:

    //*******************************************************************
    //DDR3 PHY parameters
    //*******************************************************************

    #define CMD_PHY_CTRL_SLAVE_RATIO 0x00000100
    #define CMD_PHY_INVERT_CLKOUT 0x00000001

    #define DATA_PHY_RD_DQS_SLAVE_RATIO 0x00000040
    #define DATA_PHY_FIFO_WE_SLAVE_RATIO 0x000000E9
    #define DATA_PHY_WR_DQS_SLAVE_RATIO 0x00000082
    #define DATA_PHY_WR_DATA_SLAVE_RATIO 0x000000C2

    #define DDR_IOCTRL_VALUE 0x0000018B

    //******************************************************************
    //EMIF parameters
    //******************************************************************
    #define ALLOPP_DDR3_READ_LATENCY 8
    #define ALLOPP_DDR3_SDRAM_TIMING1 0x0668A39B
    #define ALLOPP_DDR3_SDRAM_TIMING2 0x26247FDA
    #define ALLOPP_DDR3_SDRAM_TIMING3 0x50FFE21F

    #define ALLOPP_DDR3_SDRAM_CONFIG 0x61A05232
    #define ALLOPP_DDR3_REF_CTRL 0x0000093B
    #define ALLOPP_DDR3_ZQ_CONFIG 0x50077D33

     

    Regards,

    James

  • In reply to JJD:

    dear James,

    May it possible to have the updated xls spreadsheet to understand the incorrect parameter?

    Sébastien

  • In reply to Seb O:

    Dear James,

    I agree with you INVERT_CLKOUT must be 1.

    I ran again the full precedure and the EDMA test fails with the both working frequency 303MHz and 400MHz.

    I also get and strange behaviour at 400MHz using the DDR3_slave_ratio_search_auto.out program. I often obtained 0x0 as optimum value.

    ***************************************************************
        The Slave Ratio Search Program Values are...
    ***************************************************************
    PARAMETER                       MAX  |  MIN  | OPTIMUM |  RANGE    
    ***************************************************************
    DATA_PHY_RD_DQS_SLAVE_RATIO    0x000 | 0x000 |  0x000  | 0x000
    DATA_PHY_FIFO_WE_SLAVE_RATIO   0x000 | 0x000 |  0x000  | 0x000
    DATA_PHY_WR_DQS_SLAVE_RATIO    0x000 | 0x000 |  0x000  | 0x000
    DATA_PHY_WR_DATA_SLAVE_RATIO   0x000 | 0x000 |  0x000  | 0x000
    ***************************************************************

    I've managed to get something different than 0x0 only once.

    I will try the second procedure you gave me before.

    Sébastien

  • In reply to Seb O:

    dear James

    I've tested the am335x-ddr-analysis.dss as you recommended.

    When  load the script, I've got the below error.

    Is it due to the fact I use a Segger Probe?

    js:> loadJSFile C:\temp\am335x-ddr-analysis.dss
    Could not open session. No matching devices found. (C:\temp\am335x-ddr-analysis.dss#104)

  • In reply to Seb O:

    Seb, if you have just one DDR device (point to point connection), you don't have to run the software leveling algorithm.  The Ratio See spreadhsheet values will suffice.

    If the values above still do not pass the EDMA test, you may have a hardware issue.  Please send the revised GEL along with the console output.  I just want to ensure everything is input correctly.

    Can you send the DDR portion of your schematic?  Have you also followed all of the design guidelines in the AM335x datasheet?

    Yes, the Segger JTAG pod is not supported because it does not allow connection to the DAP.  In lieu of that, you can dump registers 0x4C000000-0x4C000120 with the Segger with the new configuration.

    I will send spreadsheets via email.

    Regards,

    James

  • In reply to JJD:

    dear james,

    I've receive a other spread sheet from your colleague to calculate the Gel file value.

    Then I tested the EDMA script  without using the software leveling algorithm. the script get stuck on test with the below log:

    CortxA8: Output: ****  AM335x BeagleBlack Initialization is in progress ..........
    CortxA8: Output: ****  AM335x ALL PLL Config for OPP == OPP100 is in progress .........
    CortxA8: Output: Input Clock Read from SYSBOOT[15:14]:  25MHz
    CortxA8: Output: ****  AM335x ALL ADPLL Config: CLKIN = 25MHz .........
    CortxA8: Output: ****  Going to Bypass...
    CortxA8: Output: ****  Bypassed, changing values...
    CortxA8: Output: ****  Locking ARM PLL
    CortxA8: Output: ****  Core Bypassed
    CortxA8: Output: ****  Now locking Core...
    CortxA8: Output: ****  Core locked
    CortxA8: Output: ****  DDR DPLL Bypassed
    CortxA8: Output: ****  DDR DPLL Locked
    CortxA8: Output: ****  PER DPLL Bypassed
    CortxA8: Output: ****  PER DPLL Locked
    CortxA8: Output: ****  DISP PLL Config is in progress ..........
    CortxA8: Output: ****  DISP PLL Config is DONE ..........
    CortxA8: Output: ****  AM335x ALL ADPLL Config for OPP == OPP100 - DDR3 303MHz) is Done .........
    CortxA8: Output: ****  AM335x DDR3 EMIF and PHY configuration is in progress.........
    CortxA8: Output: EMIF PRCM is in progress .......
    CortxA8: Output: EMIF PRCM Done
    CortxA8: Output: DDR PHY Configuration in progress
    CortxA8: Output: Waiting for VTP Ready .......
    CortxA8: Output: VTP is Ready!
    CortxA8: Output: DDR PHY CMD0 Register configuration is in progress .......
    CortxA8: Output: DDR PHY CMD1 Register configuration is in progress .......
    CortxA8: Output: DDR PHY CMD2 Register configuration is in progress .......
    CortxA8: Output: DDR PHY DATA0 Register configuration is in progress .......
    CortxA8: Output: DDR PHY DATA1 Register configuration is in progress .......
    CortxA8: Output: Setting IO control registers.......
    CortxA8: Output: EMIF Timing register configuration is in progress .......
    CortxA8: Output: EMIF Timing register configuration is done .......
    CortxA8: Output: DDR PHY Configuration done
    CortxA8: Output: ****  AM335x BeagleBlack Initialization is Done ******************


    CortxA8: GEL Output:

    This EDMA test consists of 8 tests.
    CortxA8: GEL Output: Write is completed Starting @0x80000000
    CortxA8: GEL Output: Write is completed Starting @0x40300000
    CortxA8: GEL Output:
    Test 1
    CortxA8: GEL Output: Write is completed Starting @0x80000000

    CortxA8: GEL Output: EDMA Transfer Start for QUEPRI 0x00000000

    My gel files

    eSOM G+ 303MHz - 01.gel

    eSOM G+ 400MHz - 01.gel

    Then I've try to run the software leveling algorithm and it get also stuck. It run automatically (while I needed to use run it manually after being loaded.) and it does ask me the value obtain from spreadsheet.

    Then I've try to run my previous gel file and I also get stuck.

    I tested with two boards and I get the same behaviour.

    Does the LoadJS command could corrupt my setup? It was the last test I did before update gel file with the xlsx file.

  • In reply to Seb O:

    Dear James,

    I looked at the GEL to know why and where the script is locked.

    It is locked in the while loop while( (RD_MEM_32(TPCC_BASE_ADDR+0x1068)&0x1) !=1 )  {  } at line 1028 in the edmaConfigure function.
    I don't know what could be the root cause!

    Sebastien

  • In reply to Seb O:

    Dear james,

    Today I worked to understand why the script get locked and why EDMA test fails.

    • Concerning locking by loop "while( (RD_MEM_32(TPCC_BASE_ADDR+0x1068)&0x1) !=1 )  {  }"

      - The workaround is to do the below step with CCS menu after each Connect to cortex A8
              > Run -> Reset -> Board Reset
              > Scripts -> Am335x System Initialization -> Am335x_BeagleBlack_Initialization
      - The different between the init done by OnConnect() function is GEL and the above sequence is the below line appears in console during initialisation
    "CortxA8: Output: PHY is READY!!"
        This line appear when the condition if((RD_MEM_32(EMIF_STATUS_REG) & 0x4) == 0x4) is true
        When initialization is done automatically on connect, the above line often does not appears in console.
      - When it does not appear, the GEL file is locked by "while( (RD_MEM_32(TPCC_BASE_ADDR+0x1068)&0x1) !=1 )  {  }" on first EDMA transfer.

        What could make EMIF_STATUS_REG reg bit 3 keep to '0' (DDR PHY Ready not ready)?

    • Concerning EDMA test failure

      - The test #1 always passes
      - For the next test (2 to 8),
          the comparison after EDMA transfer from DDR3 to internal RAM always FAILS.
          the comparison after EDMA transfer from internal RAM fails to DDR3 always PASSES.
      - So I compare the memory content in the DDR3 (0x8000_0000) and in the internal RAM (0x4030_0000).
        I found the content of internal RAM correspond to test pattern of Test 1 as the DMA transfert to DDR3 to internal RAM did not run during test 2 to 8.
      - So I updated the GEL file in order to, for each test from 1 to 8, don't use the same base address DDR3 address and same base address fir internal RAM during each DMA transfert.
        I appears that when only the internal RAM base address changes for each test, all tests PASS.   

        What could make DDR3 to internal RAM does work when two or more consecutive transfert is done at the same internal RAM base address?

     My GEL file, a bit refactored in EDMA function:  400MHz - 01.gel

    Regards


    Sébastien