Hello,
I'm using Vision SDK 3.04.00.00 on my custom 2GB board based on DRA77P; software platform is Android 8.1 (based on TI 6AO.1.1). I'm trying to include IPUMM inside Vision SDK running on IPU2 build in order to enable accelerated video playback at Android side.
At Linux (Android) side, I have 384MB of CMA memory mapped at 0xD0000000:
linux_cma_pool: linux_cma@d0000000 {
compatible = "shared-dma-pool";
reg = <0x0 0xd0000000 0x0 0x18000000>;
reusable;
linux,cma-default;
status = "okay";
};
At Vision SDK side, I've set IPUMM_INCLUDE=yes inside cfg.mk and mapped the CMA memory inside system_rsc_table_ipu.h:
#define LINUX_IPUMM_MEM 0xD0000000
#define IPU_IPUMM_MEM 0xD0000000
{
TYPE_DEVMEM,
IPU_IPUMM_MEM, LINUX_IPUMM_MEM,
(SZ_128M + SZ_256M), 0, 0, "IPU_IPUMM_MEM",
}
While playback seems to take place, I'm currently seeing a completely distorted stream on the screen, with decoding artifacts everywhere. Things seems to get a little better if I use 0xD8000000 instead of 0xD0000000 as base address for Linux CMA, but when CMA memory consumption increases the artifacts start to appear again (randomly).
Am I missing something in the configuration, or more probably in the underlying memory allocation constraints?
In attach: system_rsc_table_ipu.h and mem_segment_definition_linux.xs, plus memory reservation part of DTS.
Thank you very much
Regards,
Francesco
memory-reservation.dts.txt
/dts-v1/;
/ {
reserved_mem: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
linux_cma_pool: linux_cma@d0000000 {
compatible = "shared-dma-pool";
reg = <0x0 0xd0000000 0x0 0x18000000>;
reusable;
linux,cma-default;
status = "okay";
};
ipu1_cma_pool: ipu1_cma@9d000000 {
compatible = "shared-dma-pool";
reg = <0x0 0x9d000000 0x0 0x2000000>;
reusable;
status = "okay";
};
ipu2_cma_pool: ipu2_cma@98000000 {
compatible = "shared-dma-pool";
reg = <0x0 0x98000000 0x0 0x5000000>;
reusable;
status = "okay";
};
dsp1_cma_pool: dsp1_cma@a1000000 {
compatible = "shared-dma-pool";
reg = <0x0 0xa1000000 0x0 0x2000000>;
reusable;
status = "disabled";
};
dsp2_cma_pool: dsp2_cma@a3000000 {
compatible = "shared-dma-pool";
reg = <0x0 0xa3000000 0x0 0x2000000>;
reusable;
status = "disabled";
};
latea_pagetbl: late_pgtbl@bfc00000 {
reg = <0x0 0xbfc00000 0x0 0x0100000>;
no-map;
status = "okay";
};
cmem_ocmc: cmem@40300000 {
compatible = "shared-dma-pool";
reg = <0x0 0x40300000 0x0 0x300000>;
sram = <&ocmcram1>;
no-map;
status = "okay";
};
assets: assets@A9000000 {
reg = <0x0 0xA9000000 0x0 0x01000000>;
no-map;
status = "okay";
};
vsdk_sr1_mem: vsdk_sr1_mem@84000000 {
reg = <0x0 0x84000000 0x0 0x01000000>;
status = "okay";
};
vsdk_sr0_mem: vsdk_sr0_mem@A0000000 {
reg = <0x0 0xA0000000 0x0 0x01000000>;
status = "okay";
};
};
};
system_rsc_table_ipu.h.txt
/*
Copyright (c) [2012 - 2017] Texas Instruments Incorporated
All rights reserved not granted herein.
Limited License.
Texas Instruments Incorporated grants a world-wide, royalty-free, non-exclusive
license under copyrights and patents it now or hereafter owns or controls to
make, have made, use, import, offer to sell and sell ("Utilize") this software
subject to the terms herein. With respect to the foregoing patent license,
such license is granted solely to the extent that any such patent is necessary
to Utilize the software alone. The patent license shall not apply to any
combinations which include this software, other than combinations with devices
manufactured by or for TI ("TI Devices"). No hardware patent is licensed
hereunder.
Redistributions must preserve existing copyright notices and reproduce this
license (including the above copyright notice and the disclaimer and
(if applicable) source code license limitations below) in the documentation
and/or other materials provided with the distribution
Redistribution and use in binary form, without modification, are permitted
provided that the following conditions are met:
* No reverse engineering, decompilation, or disassembly of this software
is permitted with respect to any software provided in binary form.
* Any redistribution and use are licensed by TI for use only with TI Devices.
* Nothing shall obligate TI to provide you with source code for the software
licensed and provided to you in object code.
If software source code is provided to you, modification and redistribution of
the source code are permitted provided that the following conditions are met:
* Any redistribution and use of the source code, including any resulting
derivative works, are licensed by TI for use only with TI Devices.
* Any redistribution and use of any object code compiled from the source code
and any resulting derivative works, are licensed by TI for use only with TI
Devices.
Neither the name of Texas Instruments Incorporated nor the names of its
suppliers may be used to endorse or promote products derived from this software
without specific prior written permission.
DISCLAIMER.
THIS SOFTWARE IS PROVIDED BY TI AND TI�S LICENSORS "AS IS" AND ANY EXPRESS OR
IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL TI AND TI�S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT,
INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* ======== system_rsc_table_ipu.h ========
*
* Define the resource table entries for all IPU cores. This will be
* incorporated into corresponding base images, and used by the remoteproc
* on the host-side to allocated/reserve resources.
*
*/
#ifndef _RSC_TABLE_IPU_H_
#define _RSC_TABLE_IPU_H_
#include <xdc/std.h>
#include <xdc/cfg/global.h>
#include <ti/ipc/remoteproc/rsc_types.h>
#include <include/link_api/system_vring_config.h>
/* Number of entries in resource table */
#ifdef IPU1_LOAD_EVES
#define RSC_NUM_ENTRIES 20
#else
#define RSC_NUM_ENTRIES 19
#endif
/* IPU Memory Map */
#define L4_PERIPHERAL_L4EMU 0x54000000
#define IPU_PERIPHERAL_L4EMU 0x74000000
#define IPU_REG_SPACE_MAP1_VIRT 0x60100000
#define IPU_REG_SPACE_MAP1_PHYS 0x40100000
#define IPU_REG_SPACE_MAP1_SIZE 0x1FF00000
#define IPU_REG_SPACE_MAP2_VIRT 0x40000000
#define IPU_REG_SPACE_MAP2_PHYS 0x40000000
#define IPU_REG_SPACE_MAP2_SIZE 0x20000000
#define L3_IVAHD_CONFIG 0x5A000000
#define IPU_IVAHD_CONFIG 0x5A000000
#define L3_IVAHD_SL2 0x5B000000
#define IPU_IVAHD_SL2 0x5B000000
#define L3_TILER_MODE_0_1 0x60000000
#define IPU_TILER_MODE_0_1 0xA0000000
#define L3_TILER_MODE_2 0x70000000
#define IPU_TILER_MODE_2 0xB0000000
#define L3_TILER_MODE_3 0x78000000
#define IPU_TILER_MODE_3 0xB8000000
#define LINUX_IPUMM_MEM 0xD0000000
#define IPU_IPUMM_MEM 0xD0000000
#define IPU_MEM_TEXT 0x0
#ifdef BUILD_M4_0
#define IPU_MEM_CODE_DATA XDC_CFG_IPU1_0_CODE_DATA
#endif
#ifdef BUILD_M4_2
#define IPU_MEM_CODE_DATA XDC_CFG_IPU2_CODE_DATA
#endif
#define IPU_SR1_VIRT XDC_CFG_SR1_VIRT
#define IPU_SR1 XDC_CFG_SR1_VIRT
#define IPU_MEM_IPC_DATA XDC_CFG_IPC_DATA
#define IPU_NDK_MEM XDC_CFG_NDK_MEM
#define SYSTEM_COMMON_SHM_VIRT XDC_CFG_SYSTEM_COMMON_SHM_VIRT
#define SYSTEM_COMMON_SHM XDC_CFG_SYSTEM_COMMON_SHM_VIRT
#define EVE_MEM_VIRT XDC_CFG_EVE_MEM
#define EVE_MEM XDC_CFG_EVE_MEM
#define IPU_MEM_IPC_VRING_SIZE (SZ_1M)
#define IPU_MEM_TEXT_SIZE (SZ_1M)
#ifdef BUILD_M4_0
#define IPU_MEM_CODE_DATA_SIZE XDC_CFG_IPU1_0_CODE_DATA_SIZE
#endif
#ifdef BUILD_M4_2
#define IPU_MEM_CODE_DATA_SIZE XDC_CFG_IPU2_CODE_DATA_SIZE
#endif
#define IPU_MEM_IPC_DATA_SIZE XDC_CFG_IPC_DATA_SIZE
#define IPU_SR1_SIZE XDC_CFG_SR1_SIZE
#define IPU_NDK_MEM_SIZE XDC_CFG_NDK_MEM_SIZE
#define SYSTEM_COMMON_SHM_SIZE XDC_CFG_SYSTEM_COMMON_SHM_SIZE
#define EVE_MEM_SIZE XDC_CFG_EVE_MEM_SIZE
#define SR2_VIRT XDC_CFG_SR2_VIRT
#define SR2_PHYS XDC_CFG_SR2_VIRT
#define SR2_SIZE XDC_CFG_SR2_SIZE
/*
* Sizes of the virtqueues (expressed in number of buffers supported,
* and must be power of 2)
*/
#define IPU_RPMSG_VQ0_SIZE 256
#define IPU_RPMSG_VQ1_SIZE 256
/* flip up bits whose indices represent features we support */
#define RPMSG_IPU_C0_FEATURES 1
struct my_resource_table {
struct resource_table base;
UInt32 offset[RSC_NUM_ENTRIES]; /* Should match 'num' in actual definition */
/* rpmsg vdev entry */
struct fw_rsc_vdev rpmsg_vdev;
struct fw_rsc_vdev_vring rpmsg_vring0;
struct fw_rsc_vdev_vring rpmsg_vring1;
/* text carveout entry */
struct fw_rsc_carveout text_cout;
/* ipcdata carveout entry */
struct fw_rsc_carveout ipcdata_cout;
/* ipcdata carveout entry */
struct fw_rsc_carveout ipucodedata_cout;
/* trace entry */
struct fw_rsc_trace trace;
/* devmem entry */
struct fw_rsc_devmem devmem0;
/* devmem entry */
struct fw_rsc_devmem devmem1;
/* devmem entry */
struct fw_rsc_devmem devmem2;
/* devmem entry */
struct fw_rsc_devmem devmem3;
/* devmem entry */
struct fw_rsc_devmem devmem4;
/* devmem entry */
struct fw_rsc_devmem devmem5;
/* devmem entry */
struct fw_rsc_devmem devmem6;
/* devmem entry */
struct fw_rsc_devmem devmem7;
/* devmem entry */
struct fw_rsc_devmem devmem8;
/* devmem entry */
struct fw_rsc_devmem devmem9;
/* devmem entry */
struct fw_rsc_devmem devmem10;
/* devmem entry */
struct fw_rsc_devmem devmem11;
#ifdef IPU1_LOAD_EVES
/* devmem entry */
struct fw_rsc_devmem devmem12;
#endif
/* devmem entry */
struct fw_rsc_devmem devmem13;
/* devmem entry */
struct fw_rsc_devmem devmem14;
};
extern char ti_trace_SysMin_Module_State_0_outbuf__A;
#define TRACEBUFADDR (UInt32)&ti_trace_SysMin_Module_State_0_outbuf__A
#pragma DATA_SECTION(ti_ipc_remoteproc_ResourceTable, ".resource_table")
#pragma DATA_ALIGN(ti_ipc_remoteproc_ResourceTable, 4096)
struct my_resource_table ti_ipc_remoteproc_ResourceTable = {
1, /* we're the first version that implements this */
RSC_NUM_ENTRIES, /* number of entries in the table */
0, 0, /* reserved, must be zero */
/* offsets to entries */
{
offsetof(struct my_resource_table, rpmsg_vdev),
offsetof(struct my_resource_table, text_cout),
offsetof(struct my_resource_table, ipcdata_cout),
offsetof(struct my_resource_table, ipucodedata_cout),
offsetof(struct my_resource_table, trace),
offsetof(struct my_resource_table, devmem0),
offsetof(struct my_resource_table, devmem1),
offsetof(struct my_resource_table, devmem2),
offsetof(struct my_resource_table, devmem3),
offsetof(struct my_resource_table, devmem4),
offsetof(struct my_resource_table, devmem5),
offsetof(struct my_resource_table, devmem6),
offsetof(struct my_resource_table, devmem7),
offsetof(struct my_resource_table, devmem8),
offsetof(struct my_resource_table, devmem9),
offsetof(struct my_resource_table, devmem10),
offsetof(struct my_resource_table, devmem11),
#ifdef IPU1_LOAD_EVES
offsetof(struct my_resource_table, devmem12),
#endif
offsetof(struct my_resource_table, devmem13),
offsetof(struct my_resource_table, devmem14),
},
/* rpmsg vdev entry */
{
TYPE_VDEV, VIRTIO_ID_RPMSG, 0,
RPMSG_IPU_C0_FEATURES, 0, 0, 0, 2, { 0, 0 },
/* no config data */
},
/* the two vrings */
{ IPU_MEM_RPMSG_VRING0, 4096, IPU_RPMSG_VQ0_SIZE, 1, 0 },
{ IPU_MEM_RPMSG_VRING1, 4096, IPU_RPMSG_VQ1_SIZE, 2, 0 },
{
TYPE_CARVEOUT,
IPU_MEM_TEXT, 0,
IPU_MEM_TEXT_SIZE, 0, 0, "IPU_MEM_TEXT",
},
{
TYPE_CARVEOUT,
IPU_MEM_IPC_DATA, 0,
IPU_MEM_IPC_DATA_SIZE, 0, 0, "IPU_MEM_IPC_DATA",
},
{
TYPE_CARVEOUT,
IPU_MEM_CODE_DATA, 0,
IPU_MEM_CODE_DATA_SIZE, 0, 0, "IPU_MEM_CODE_DATA",
},
{
TYPE_TRACE, TRACEBUFADDR, 0x8000, 0, "trace:sysm3",
},
{
TYPE_DEVMEM,
IPU_MEM_IPC_VRING, IPU_PHYS_MEM_IPC_VRING,
IPU_MEM_IPC_VRING_SIZE, 0, 0, "IPU_MEM_IPC_VRING",
},
{
TYPE_DEVMEM,
IPU_TILER_MODE_0_1, L3_TILER_MODE_0_1,
SZ_1M, 0, 0, "IPU_TILER_MODE_0_1",
},
{
TYPE_DEVMEM,
IPU_TILER_MODE_2, L3_TILER_MODE_2,
SZ_128M, 0, 0, "IPU_TILER_MODE_2",
},
{
TYPE_DEVMEM,
IPU_TILER_MODE_3, L3_TILER_MODE_3,
SZ_128M, 0, 0, "IPU_TILER_MODE_3",
},
{
TYPE_DEVMEM,
IPU_REG_SPACE_MAP1_VIRT, IPU_REG_SPACE_MAP1_PHYS,
IPU_REG_SPACE_MAP1_SIZE, 0, 0, "IPU_REG_SPACE_MAP1",
},
{
TYPE_DEVMEM,
IPU_REG_SPACE_MAP2_VIRT, IPU_REG_SPACE_MAP2_PHYS,
IPU_REG_SPACE_MAP2_SIZE, 0, 0, "IPU_REG_SPACE_MAP2",
},
{
TYPE_DEVMEM,
IPU_PERIPHERAL_L4EMU, L4_PERIPHERAL_L4EMU,
SZ_16M, 0, 0, "IPU_PERIPHERAL_L4EMU",
},
{
TYPE_DEVMEM,
IPU_IVAHD_CONFIG, L3_IVAHD_CONFIG,
SZ_16M, 0, 0, "IPU_IVAHD_CONFIG",
},
{
TYPE_DEVMEM,
IPU_IVAHD_SL2, L3_IVAHD_SL2,
SZ_16M, 0, 0, "IPU_IVAHD_SL2",
},
{
TYPE_DEVMEM,
SYSTEM_COMMON_SHM_VIRT, SYSTEM_COMMON_SHM,
SYSTEM_COMMON_SHM_SIZE, 0, 0, "SYSTEM_COMMON_SHM",
},
{
TYPE_DEVMEM,
IPU_SR1_VIRT, IPU_SR1,
IPU_SR1_SIZE, 0, 0, "IPU_SR1",
},
{
TYPE_DEVMEM,
IPU_NDK_MEM, IPU_NDK_MEM,
IPU_NDK_MEM_SIZE, 0, 0, "IPU_NDK_MEM",
},
#ifdef IPU1_LOAD_EVES
{
TYPE_DEVMEM,
EVE_MEM_VIRT, EVE_MEM,
EVE_MEM_SIZE, 0, 0, "EVE_MEM",
},
#endif
{
TYPE_DEVMEM,
SR2_VIRT, SR2_PHYS,
SR2_SIZE, 0, 0, "SR2_MEM",
},
{
TYPE_DEVMEM,
IPU_IPUMM_MEM, LINUX_IPUMM_MEM,
(SZ_128M + SZ_256M), 0, 0, "IPU_IPUMM_MEM",
},
};
#endif /* _RSC_TABLE_IPU_H_ */
mem_segment_definition_linux.xs.txt
/*
*******************************************************************************
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
* ALL RIGHTS RESERVED
*
*******************************************************************************
*/
/*
* ======== mem_segment_definition.xs ========
* ======== Single file for the memory map configuration of all cores =========
*/
KB=1024;
MB=KB*KB;
/* Allocation of cores' internal memory resources */
DSP1_L2_SRAM_ADDR = 0x40800000;
DSP1_L2_SRAM_SIZE = 288*KB;
DSP2_L2_SRAM_ADDR = 0x41000000;
DSP2_L2_SRAM_SIZE = 288*KB;
EVE1_SRAM_ADDR = 0x42000000;
EVE1_SRAM_SIZE = 1*MB;
EVE2_SRAM_ADDR = 0x42100000;
EVE2_SRAM_SIZE = 1*MB;
/* DDR3 Memory map 2GB */
/*************************
Required-by Size Address Used-for Cacheable
A15-Linux 64MB 0x80000000
SR1 + NDK , 16MB 0x84000000 SR1+NDK Yes to All cores
IPU2-Bios 80MB 0x98000000 Vision-SDK FWK (12 MB Hole)
IPU1-Bios 32MB 0x9D000000 IPU2 Core Yes to IPU1
DSP1-Bios 64MB 0xA1000000 RADIO (+ Analytic algos) 16MB non-cacheable - required by RADIO
DSP2-Bios 32MB 0xA3000000 SRV Algos Yes to DSP2
A15, IPU1/2, DSP1/2 32MB 0xA0000000 SR0 No to All cores
EVE 64MB 0xA5000000
SR2_BASE_ADDR 0xA9000000
A15-Linux 0xC0000000(End of Interleaving)
*************************/
DDR3_ADDR = 0x80000000;
DDR3_SIZE = 1024*MB;
DDR3_LINUX_MEM_OFFSET = 64*MB;
/* First 512 MB - cached */
DDR3_BASE_ADDR_0 = 0x80000000;
DDR3_BASE_SIZE_0 = 448*MB + DDR3_LINUX_MEM_OFFSET;
/* The start address of the second mem section should be 16MB aligned.
* This alignment is a must as a single 16MB mapping is used for EVE
* to map SR0, REMOTE_LOG_MEM sections.
* tlb_config_eveX.c need to be modified otherwise
*/
DDR3_BASE_ADDR_1 = 0xA0000000;
DDR3_BASE_SIZE_1 = 512*MB;
/* Address and Size definitions of different components running on different cores */
NDK_START_ADDR = DDR3_BASE_ADDR_0 + DDR3_LINUX_MEM_OFFSET;
NDK_MEM_SIZE = 2*MB
SR1_FRAME_BUFFER_SIZE = 10*MB;
SR1_BUFF_ECC_ASIL_SIZE = 4*KB;
SR1_BUFF_ECC_QM_SIZE = 4*KB;
SR1_BUFF_NON_ECC_ASIL_SIZE = 4*KB;
var ipummSupport = java.lang.System.getenv("IPUMM_INCLUDE");
/* Keep both IPU1 & IPU2 with same code & data sizes,
* this allows to select any IPU subsystem as primary IPU core */
IPU2_START_ADDR = 0x98000000;
IPU2_CODE_SIZE = 10*MB;
if (ipummSupport == "yes") {
IPU2_DATA_SIZE = 60*MB;
}
else {
IPU2_DATA_SIZE = 20*MB;
}
IPU1_START_ADDR = 0x9D000000;
IPU1_0_CODE_SIZE = 8*MB;
IPU1_0_DATA_SIZE = 21*MB;
DSP1_START_ADDR = 0xA1000000;
DSP1_CODE_SIZE = 2*MB;
DSP1_DATA_SIZE = 24*MB;
DSP2_START_ADDR = 0xA3000000;
DSP2_CODE_SIZE = 2*MB;
DSP2_DATA_SIZE = 10*MB;
/* The start address of the second mem section should be 16MB aligned.
* This alignment is a must as a single 16MB mapping is used for EVE
* to map SR0, REMOTE_LOG_MEM sections.
* tlb_config_eveX.c need to be modified otherwise
*
* size of REMOTE_LOG_SIZE+SYSTEM_IPC_SHM_SIZE+LINK_STATS_SIZE+
* HDVPSS_DESC_SIZE+SR0_SIZE
* MUST be a multiple of MB
*/
REMOTE_LOG_SIZE = 256*KB;
SYSTEM_IPC_SHM_SIZE = 512*KB;
LINK_STATS_SIZE = 512*KB;
HDVPSS_DESC_SIZE = 1024*KB;
SR0_SIZE = 1024*KB;
TRACE_BUF_LEN = 384*KB;
EXC_DATA_LEN = 64*KB;
PM_DATA_LEN = 512*KB;
OPENVX_SHM_SIZE = 2*MB;
/* The start address of EVE memory must be 16MB aligned. */
EVE_START_ADDR = 0xA5000000;
/* EVE vecs space should be align with 16MB boundary, and if possible try to fit
* the entire vecs+code+data in 16MB section. In this case a single TLB map would
* be enough to map vecs+code+data of an EVE.
* tlb_config_eveX.c need to be modified if any of these EVE memory sections or
* SR1_FRAME_BUFFER_MEM section is modified.
*/
EVE1_VECS_SIZE = 0.5*MB;
EVE1_CODE_SIZE = 2*MB;
EVE1_DATA_SIZE =13.5*MB;
EVE2_VECS_SIZE = 0.5*MB;
EVE2_CODE_SIZE = 2*MB;
EVE2_DATA_SIZE =13.5*MB;
TOTAL_MEM_SIZE = (DDR3_SIZE);
/* A single Linux mem hole is used for both NDK MEM and SR1_FRAME MEM
* So both of these sections should be one after another without any gap
*/
NDK_MEM_ADDR = NDK_START_ADDR
SR1_BUFF_ECC_ASIL_ADDR = NDK_MEM_ADDR + NDK_MEM_SIZE;
SR1_BUFF_ECC_QM_ADDR = SR1_BUFF_ECC_ASIL_ADDR + SR1_BUFF_ECC_ASIL_SIZE;
SR1_BUFF_NON_ECC_ASIL_ADDR = SR1_BUFF_ECC_QM_ADDR + SR1_BUFF_ECC_QM_SIZE;
SR1_FRAME_BUFFER_ADDR = SR1_BUFF_NON_ECC_ASIL_ADDR + SR1_BUFF_NON_ECC_ASIL_SIZE;
IPU2_CODE_ADDR = IPU2_START_ADDR;
IPU2_DATA_ADDR = IPU2_CODE_ADDR + IPU2_CODE_SIZE;
DSP1_CODE_ADDR = DSP1_START_ADDR;
DSP1_DATA_ADDR = DSP1_CODE_ADDR + DSP1_CODE_SIZE;
IPU1_0_CODE_ADDR = IPU1_START_ADDR;
IPU1_0_DATA_ADDR = IPU1_0_CODE_ADDR + IPU1_0_CODE_SIZE;
DSP2_CODE_ADDR = DSP2_START_ADDR;
DSP2_DATA_ADDR = DSP2_CODE_ADDR + DSP2_CODE_SIZE;
/* Non Cached Section for IPU1 */
/* The start address of the second mem section should be 16MB aligned.
* This alignment is a must as a single 16MB mapping is used for EVE
* to map SR0, REMOTE_LOG_MEM sections.
* tlb_config_eveX.c need to be modified otherwise
*/
SR0_ADDR = DDR3_BASE_ADDR_1 + 1*MB; /* Leaving 1MB for virtqueue of DSP - this is hardcoded in ipc virqueue */
REMOTE_LOG_ADDR = SR0_ADDR + SR0_SIZE;
LINK_STATS_ADDR = REMOTE_LOG_ADDR + REMOTE_LOG_SIZE;
SYSTEM_IPC_SHM_ADDR = LINK_STATS_ADDR + LINK_STATS_SIZE;
HDVPSS_DESC_ADDR = SYSTEM_IPC_SHM_ADDR + SYSTEM_IPC_SHM_SIZE;
if(java.lang.System.getenv("OPENVX_INCLUDE")=="yes")
{
OPENVX_SHM_ADDR = HDVPSS_DESC_ADDR + HDVPSS_DESC_SIZE;
TRACE_BUF_BASE = OPENVX_SHM_ADDR + OPENVX_SHM_SIZE;
}
else
{
TRACE_BUF_BASE = HDVPSS_DESC_ADDR + HDVPSS_DESC_SIZE;
}
EXC_DATA_BASE = TRACE_BUF_BASE + TRACE_BUF_LEN;
PM_DATA_BASE = EXC_DATA_BASE + EXC_DATA_LEN;
/* EVE vecs space should be align with 16MB boundary, and if possible try to fit
* the entire vecs+code+data in 16MB section. In this case a single TLB map would
* be enough to map vecs+code+data of an EVE.
* tlb_config_eveX.c need to be modified if any of these EVE memory sections or
* SR1_FRAME_BUFFER_MEM section is modified.
*/
EVE1_VECS_ADDR = EVE_START_ADDR
EVE1_CODE_ADDR = EVE1_VECS_ADDR + EVE1_VECS_SIZE;
EVE1_DATA_ADDR = EVE1_CODE_ADDR + EVE1_CODE_SIZE;
EVE2_VECS_ADDR = EVE1_DATA_ADDR + EVE1_DATA_SIZE;
EVE2_CODE_ADDR = EVE2_VECS_ADDR + EVE2_VECS_SIZE;
EVE2_DATA_ADDR = EVE2_CODE_ADDR + EVE2_CODE_SIZE;
var A15TargetOS = java.lang.System.getenv("A15_TARGET_OS");
if (A15TargetOS == "Qnx") {
/* Shared Region handled by A15 HLOS Qnx*/
SR2_BASE_ADDR = 0xBA300000;
SR2_SIZE = 90*MB;
}
else {
/* Shared Region handled by A15 HLOS Linux*/
SR2_BASE_ADDR = 0xA9000000;
SR2_SIZE = 16*MB;
}
function getMemSegmentDefinition_external(core)
{
var memory = new Array();
var index = 0;
memory[index++] = ["IPU1_0_CODE_MEM", {
comment : "IPU1_0_CODE_MEM",
name : "IPU1_0_CODE_MEM",
base : IPU1_0_CODE_ADDR,
len : IPU1_0_CODE_SIZE
}];
memory[index++] = ["IPU1_0_DATA_MEM", {
comment : "IPU1_0_DATA_MEM",
name : "IPU1_0_DATA_MEM",
base : IPU1_0_DATA_ADDR,
len : IPU1_0_DATA_SIZE
}];
memory[index++] = ["NDK_MEM", {
comment : "NDK_MEM",
name : "NDK_MEM",
base : NDK_MEM_ADDR,
len : NDK_MEM_SIZE
}];
memory[index++] = ["IPU2_CODE_MEM", {
comment : "IPU2_CODE_MEM",
name : "IPU2_CODE_MEM",
base : IPU2_CODE_ADDR,
len : IPU2_CODE_SIZE
}];
memory[index++] = ["IPU2_DATA_MEM", {
comment : "IPU2_DATA_MEM",
name : "IPU2_DATA_MEM",
base : IPU2_DATA_ADDR,
len : IPU2_DATA_SIZE
}];
memory[index++] = ["DSP1_CODE_MEM", {
comment : "DSP1_CODE_MEM",
name : "DSP1_CODE_MEM",
base : DSP1_CODE_ADDR,
len : DSP1_CODE_SIZE
}];
memory[index++] = ["DSP1_DATA_MEM", {
comment : "DSP1_DATA_MEM",
name : "DSP1_DATA_MEM",
base : DSP1_DATA_ADDR,
len : DSP1_DATA_SIZE
}];
memory[index++] = ["DSP2_CODE_MEM", {
comment : "DSP2_CODE_MEM",
name : "DSP2_CODE_MEM",
base : DSP2_CODE_ADDR,
len : DSP2_CODE_SIZE
}];
memory[index++] = ["DSP2_DATA_MEM", {
comment : "DSP2_DATA_MEM",
name : "DSP2_DATA_MEM",
base : DSP2_DATA_ADDR,
len : DSP2_DATA_SIZE
}];
memory[index++] = ["EVE1_VECS_MEM", {
comment : "EVE1_VECS_MEM",
name : "EVE1_VECS_MEM",
base : EVE1_VECS_ADDR,
len : EVE1_VECS_SIZE
}];
memory[index++] = ["EVE1_CODE_MEM", {
comment : "EVE1_CODE_MEM",
name : "EVE1_CODE_MEM",
base : EVE1_CODE_ADDR,
len : EVE1_CODE_SIZE
}];
memory[index++] = ["EVE1_DATA_MEM", {
comment : "EVE1_DATA_MEM",
name : "EVE1_DATA_MEM",
base : EVE1_DATA_ADDR,
len : EVE1_DATA_SIZE
}];
memory[index++] = ["EVE2_VECS_MEM", {
comment : "EVE2_VECS_MEM",
name : "EVE2_VECS_MEM",
base : EVE2_VECS_ADDR,
len : EVE2_VECS_SIZE
}];
memory[index++] = ["EVE2_CODE_MEM", {
comment : "EVE2_CODE_MEM",
name : "EVE2_CODE_MEM",
base : EVE2_CODE_ADDR,
len : EVE2_CODE_SIZE
}];
memory[index++] = ["EVE2_DATA_MEM", {
comment : "EVE2_DATA_MEM",
name : "EVE2_DATA_MEM",
base : EVE2_DATA_ADDR,
len : EVE2_DATA_SIZE
}];
memory[index++] = ["SR1_FRAME_BUFFER_MEM", {
comment : "SR1_FRAME_BUFFER_MEM",
name : "SR1_FRAME_BUFFER_MEM",
base : SR1_FRAME_BUFFER_ADDR,
len : SR1_FRAME_BUFFER_SIZE
}];
memory[index++] = ["SR1_BUFF_ECC_ASIL_MEM", {
comment : "SR1_BUFF_ECC_ASIL_MEM",
name : "SR1_BUFF_ECC_ASIL_MEM",
base : SR1_BUFF_ECC_ASIL_ADDR,
len : SR1_BUFF_ECC_ASIL_SIZE
}];
memory[index++] = ["SR1_BUFF_ECC_QM_MEM", {
comment : "SR1_BUFF_ECC_QM_MEM",
name : "SR1_BUFF_ECC_QM_MEM",
base : SR1_BUFF_ECC_QM_ADDR,
len : SR1_BUFF_ECC_QM_SIZE
}];
memory[index++] = ["SR1_BUFF_NON_ECC_ASIL_MEM", {
comment : "SR1_BUFF_NON_ECC_ASIL_MEM",
name : "SR1_BUFF_NON_ECC_ASIL_MEM",
base : SR1_BUFF_NON_ECC_ASIL_ADDR,
len : SR1_BUFF_NON_ECC_ASIL_SIZE
}];
memory[index++] = ["SR0", {
comment : "SR0",
name : "SR0",
base : SR0_ADDR,
len : SR0_SIZE
}];
memory[index++] = ["HDVPSS_DESC_MEM", {
comment : "HDVPSS_DESC_MEM",
name : "HDVPSS_DESC_MEM",
base : HDVPSS_DESC_ADDR,
len : HDVPSS_DESC_SIZE
}];
memory[index++] = ["REMOTE_LOG_MEM", {
comment : "REMOTE_LOG_MEM",
name : "REMOTE_LOG_MEM",
base : REMOTE_LOG_ADDR,
len : REMOTE_LOG_SIZE
}];
memory[index++] = ["LINK_STATS_MEM", {
comment : "LINK_STATS_MEM",
name : "LINK_STATS_MEM",
base : LINK_STATS_ADDR,
len : LINK_STATS_SIZE
}];
memory[index++] = ["SYSTEM_IPC_SHM_MEM", {
comment : "SYSTEM_IPC_SHM_MEM",
name : "SYSTEM_IPC_SHM_MEM",
base : SYSTEM_IPC_SHM_ADDR,
len : SYSTEM_IPC_SHM_SIZE
}];
if(java.lang.System.getenv("OPENVX_INCLUDE")=="yes")
{
memory[index++] = ["OPENVX_SHM_MEM", {
comment: "OPENVX_SHM_MEM",
name: "OPENVX_SHM_MEM",
base: OPENVX_SHM_ADDR,
len: OPENVX_SHM_SIZE
}];
}
xdc.print("# !!! Core is [" + core + "] !!!" );
memory[index++] = ["DSP1_L2_SRAM", {
comment: "DSP1_L2_SRAM",
name: "DSP1_L2_SRAM",
base: DSP1_L2_SRAM_ADDR,
len: DSP1_L2_SRAM_SIZE
}];
memory[index++] = ["DSP2_L2_SRAM", {
comment: "DSP2_L2_SRAM",
name: "DSP2_L2_SRAM",
base: DSP2_L2_SRAM_ADDR,
len: DSP2_L2_SRAM_SIZE
}];
memory[index++] = ["TRACE_BUF", {
comment: "TRACE_BUF",
name: "TRACE_BUF",
base: TRACE_BUF_BASE,
len: TRACE_BUF_LEN,
}];
memory[index++] = ["EXC_DATA", {
comment: "EXC_DATA",
name: "EXC_DATA",
base: EXC_DATA_BASE,
len: EXC_DATA_LEN,
}];
memory[index++] = ["PM_DATA", {
comment: "PM_DATA",
name: "PM_DATA",
base: PM_DATA_BASE,
len: PM_DATA_LEN,
}];
memory[index++] = ["SR2_MEM", {
comment: "SR2_MEM",
name: "SR2_MEM",
base: SR2_BASE_ADDR,
len: SR2_SIZE,
}];
return (memory);
}
