PROCESSOR-SDK-AM65X: Frequency change not working

Hello user5119396,

Refer to the below e2e post:

Regards,
Pavel

Hello Pavel,

Thanks for the quick update and info, but this won't fix the issue unfortunately.

Hello,

As of Linux SDK 6.0, we do not support power management options on AM65x in Linux.

In a future release, we will add support for selecting the OPPs at boot time (ARM core speeds 800 MHz, 1GHz and 1.1 GHz). Let me check to see if there is a timeline yet for when TI will start supporting changing the ARM core speeds.

Regards,

Nick

Hello,

I apologize for the delay. I should have a better timeline later this week.

Regards,

Nick

No problem, take your time. Thanks.

I apologize for the delay. I should have an answer later this week.

Regards,

Nick

Hello,

I thought this discussion was only about changing the clock frequency, and I realized that might not have been the whole question. To clarify: Were you also asking how to properly initialize two different CPU clusters?

Regards,

Nick

Hi Nick,
The original issue was about updating CPU frequencies for both clusters and it seems that only one was updated.
But we have already implemented a patch and I suppose you have got it, right?
Now, we are waiting for your confirmation and maybe integrate it into the next release.
Thank you.

Hello,

Please see updates to 2) in my previous post. I am still working on 1).

Regards,

Nick

Hi Nick,

Thank you for the support.

This is our DTS patch for frequency change, and we have tested via CPU benchmark tool

and it seems to work. May be you could help to review it.

@@ -27,6 +27,7 @@
 	aliases {
 		remoteproc0 = &sysctrler;
 		remoteproc1 = &a53_0;
+		remoteproc2 = &a53_2;
 	};
 
 	a53_0: a53@0 {
@@ -36,13 +37,27 @@
 				<&k3_pds 202 TI_SCI_PD_SHARED>;
 		resets = <&k3_reset 202 0>;
 		assigned-clocks = <&k3_clks 202 0>;
-		assigned-clock-rates = <800000000>;
+		assigned-clock-rates = <1000000000>;
 		ti,sci = <&dmsc>;
 		ti,sci-proc-id = <32>;
 		ti,sci-host-id = <10>;
 		u-boot,dm-spl;
 	};
 
+	a53_2: a53@2 {
+		compatible = "ti,am654-rproc";
+		reg = <0x0 0x00a90000 0x0 0x10>;
+		power-domains = <&k3_pds 61 TI_SCI_PD_SHARED>,
+				<&k3_pds 204 TI_SCI_PD_SHARED>;
+		resets = <&k3_reset 204 0>;
+		assigned-clocks = <&k3_clks 204 0>;
+		assigned-clock-rates = <1000000000>;
+		ti,sci = <&dmsc>;
+		ti,sci-proc-id = <34>;
+		ti,sci-host-id = <12>;
+		u-boot,dm-spl;
+	};
+
 	vtt_supply: vtt_supply {
 		compatible = "regulator-gpio";
 		regulator-name = "vtt";
diff --git a/source/u-boot/arch/arm/mach-k3/common.c b/source/u-boot/arch/arm/mach-k3/common.c
index ccb1d05f..11cacc65 100644
--- a/source/u-boot/arch/arm/mach-k3/common.c
+++ b/source/u-boot/arch/arm/mach-k3/common.c
@@ -82,6 +82,12 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
 	release_resources_for_core_shutdown();
 
 	debug("Finalizing core shutdown...\n");
+
+	ret = rproc_dev_init(2);
+	if (ret)
+		panic("%s: ATF failed to initialize on rproc (%d)\n", __func__,
+		      ret);
+
 	while (1)
 		asm volatile("wfe");
 }

Best Regards,

Le

Hello Le,

I apologize for the delayed response. A tornado hit my work a week ago, and I still do not have access to my Linux machine or any of my boards. I am not sure when my work area will re-open, so responses may be delayed for the next several weeks.

How to see the Linux core frequencies at runtime: 

Note that I have not been able to test this code, so it might not work.

Try adding a dummy node in the kernel device tree to access the CPU frequencies. You should then be able to find the entries under the clock debugfs.

e.g., 

k3-am654.dtsi
/ {
...
+       dummy {
+               clocks = <&k3_clks 202 0>, <&k3_clks 204 0>;
+       };
  };

And then after booting the board, I would expect to be able to do something like

cd /sys/kernel/debug/clk/clk\:202\:0
cat clk_rate

Regards,

Nick

Hello Nick,

No problem, please take care and keep safe.

Meanwhile, I have found the clk value under /sys/kernel/debug/clk. But I suppose this only reflects the value in DTS but not actually calculated from the pll registers, right?

Right now, we are using dhrystone benchmark to infer that we are on the right track.

Thank you.

Best Regards,

Le

Hello Le,

clk value: I am checking on this.

code review: The dts patch looks ok. But why did you define everything for core2 in u-boot instead of just adding a second entry under the assigned-clocks for a53_0?

Regards,

Nick

clk value:

the value under /sys/kernel/debug/clk is queried from sysfw at runtime. First, the kernel calls sysfs to attempt to program the frequency values from the assigned-clock values. Then the kernel queries to see what the actual frequency is.

Regards,

Nick

Hi Nick,

Our intention is to separate two a53 clusters. I suppose the "_0" means the first cluster, so added another one.

Best Regards,

Le

Hello Le,

The developer told me that two clusters would be initialized by passing in two clocks as per the code in my October 16 post.

He says your patch looks ok (without testing it). However, the data in a53_2 is not used for anything, and he says there might be side effects of calling rproc init for a53_2.

Regards,

Nick