Other Parts Discussed in Thread: OMAPL138
Hello:
I'm reviewing an old OMAP-L138 design which uses a MT47H32M16HR DDR2 memory, where from time to time apperas certain issues that are attributed to the signal integrity.
So that I'm checking the design, my main corcern are the DQ(15:0) lines, which are bidirectional, I want to make sure that in:
WRITE CYCLES
1) OMAP-L138:
DQ(15:0) Output drivers is matched to 50 Ohms and don't need a serial resistor.
2) MT47H32M16HR DDR2 memory:
DQ(15:0) lines include ODT terminations that can be activated through the SDCR DDR2TERM(1:0) register. What is the recommended TI configuration? 50Ohms?
READ CYCLES
1) OMAP-L138:
doesn't OMAP-L138 include any ODT?
2) MT47H32M16HR DDR2 memory:
which are the recommended signal strength, selected by SDCR DDRDRIVE(1:0) register when there is a 22 ohmios serial resistor?
In general I would like to confirm the following datasheet statements:
- "6.11.3.9 No terminations of any kind are required to meet the signal integrity and overshoot requirements" . Why are 22ohm terminal resistor are used in all the DDR2 lines of the OMAP.L138/C6748 LC Dev Kit ?
- is omapl138_zwt.ibs the latest IBIS model?
Thanks.
K.M