DRA80M: What is RGMII series resistor value and absolute maximum ratings
Part Number: TMDX654GPEVM
We have custom designed a development platform based on AM6548 SoC. This platform is designed to support two Gigabit Ethernet ports via PRG1_RGMII1 and PRG2_RGMII2.
We have followed the series termination on TX and RX lines as per the recommendation. PRG1_RGMII1, PRG2_RGMII2 is connected to 1.8V and 3.3V IO levels respectively.
Here are our observations on RGMII port validation:
1) Single port loop back on MDI interface is working fine at 1Gbps. (Cable loop back)
2) Port to port loop back at 100Mbps is working without any throughput issues.
3) On few of our development platform, Port to port loop back at 1Gbps is failing to transmit few packets of data. With diagnostic code, on transmitting 300 packets of data we observed PRG2_RGMII2 receives 294 packets, missing 6 packets. Also, we have tested with various delay settings on RGMII_RX_DELAY_CTRL register. Hardware strapping option is designed to set delay to 2nS.
As stated in the above query, does operating at 3.3V cause throughput issue.
Could you please share your thoughts on this.
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