Dear Champs,
I'm looking for the 'PRU-UART FW design guide' document to understand PRU-UART FW, but could not find it in the Processor RTOS SDK.
Could you please share the document?
And could you please let me know the detailed scenario how Cortex-A9 ARM core can get data from PRU-UART and how much redundant latency can be expected in this case without any data loss when there are 1 Mbps data communicated through PRU-UART?
Thanks and Best Regards,
SI.