RTOS/66AK2H12: MSMC Caching attributes
Part Number: 66AK2H12
Tool/software: Code Composer Studio
I want to configure a shared memory(MSMCRAM) .
1. I am using multi core processor i.e, i want to use two cores I have two different projects one project in core_0 and another in core_1, in core_0 have some data that data should be used in core_1 and again that data is used by core_0 for that I am using MSM RAM to access the data from both the processor.
2. The address is defined in data sheet for MSMRAM from 0XC000000 to C5FFFFF can I use this memory by using pointers ? OR I should configure any other register ?
3. I am using the address directly but that data is not fetched by that address in both the cores, should I configure any memory of MSM in .cfg file? and .c fie?
Can anyone suggest me how to configure MSMRAM and share any example projects if you have to refer .
THANKS AND REGARDS
KAVYA M U
MSMC can be shared by multiple cores. You can use pointer to the address. We have a multi-core demo:
"3. I am using the address directly but that data is not fetched by that address in both the cores, should I configure any memory of MSM in .cfg file? and .c fie?"=====>I don't understand what you mean, the simplest way :
*(unsigned int*)0x0c00_0000 = value; //for write
a = *(unsigned int*)0x0c00_0000; //for read
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In reply to lding:
Thank you for the response,
I am doing the same thing what you mentioned above for the CORE0 AND CORE1 assigned address value also and in both the cores configured both the address.
a=(unsigned int*)0x0c00_0004; a=10; // CORE0
b=(unsigned int*)0x0c00_0008; // CORE1
b should be change right? address of shared memory should be used by both the cores .
0x0c00_0008 this address nothing is changed, i am running both the cores , again i want use the b data again in CORE0. the data is big in my real condition this is just a example .
any wrong i configured please let me know.
KAVYA M U
In reply to kavya mu:
DSP doesn't maintain the cache coherence between different masters. MSMC is cached into L1D.
THANKS for the response
I attached the program file go throw ones i can't able to access directly the MSM memory please let me know if any thing wrong I am doing or I have to configure the MPAX register or any cache invalidate, write back invalidate i have to do.
I am using core0 and core1 from both the cores i have to access the MSM memory parallel , any other method is there to access the data?
can i acces directly the memory how i am using in the program like that help me in this problem.
0x0bc0,,,,,region is not MSMC memory, but it is MSMC configuration registers. Please use 0x0c00_0000 for MSMC memory.
Sorry I sent different program but the same program I used 0x0c00_0000 this address only but the MSMC memory is not configuring please let me know i have to configure any MPAX register in Corepac C66xx device?
Its an immediate requirement let me know....
Can you upload the CCS project here? Then describe what core(s) you run it? What result you expect and what you saw? Then I can look at it.
Thanks for the response
1) This is the program which i have debug in this core0 i was given a value datatx = 5 its in the memory showing in program pic.
2) That same data datatx i was using in core1 that is datarx=datatx+5; but the data i am not able to access from core1 . see the memory locations also...
This is the program so now can you tell me where i am doing mistake...
You CCS memory view is with L1D cache and L2 cache checked in the box. So what you saw is in the cache, not in the MSMC memory. You can uncheck those two boxes to understand the difference between cached memory and uncached memory.
In core A, when you do write, you need do:
In core B, when you want to read a data (which is written by core A), you need do:
See pdk_k2hk_4_0_xx\packages\ti\csl\csl_cacheAux.h for those functions.
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