Tool/software: Code Composer Studio
Hello,
Environment:
- Hardware: AM65x IDK
- Software: ti-processor-sdk-rtos-am65xx-evm-06_01_00_08
We have conducted the same experiment in this post without TI-RTOS. This time we took your advice and put everything inside TCMA and TCMB.
The experiment is like:
- we utilize the example code <PDK>\packages\ti\csl\test\dmTimerUt\
- create a timer which generates interrupts every 125us
- get CPU tick returned by CSL_armR5PmuReadCntr() in the beginning of the Timer ISR
- calculate the difference time between every two interrupts
The theoretical value of the difference time should be 125us; however, after running the program for one hour we get the min value is 124.035 us and max value is 126.045 us which shows the jitter is around 2.01 (126.045 - 124.035) us.
Are the numbers reasonable? Or is there anything I understand or configure wrong?
The source code:
The linker file: