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USB_OTG_VBUS input timing for MCIMX6 series

Other Parts Discussed in Thread: TPS6521815

First, I explain my application.

+28V input and converted to +3.3V and +5V.

+3.3V supplies Ethernet-switch-IC and pull-ups for I.MX6.

+5V supplies only USB_OTG/H1_VSUB for i.MX6.

First, +5V enables. Several msec later, +3.3V enables.

I have figures, but I cannot attach it.

Problem:

Any voltage leaks from any voltage source and +3.3V line floats around 0.5V to 1.6V during the period from +5V- enable to +3.3V-enable. On the other hand, our Ethernet-IC can work at Vcc=1.62V, minimum voltage.

Sometimes, Ethernet-IC works abnormally.

My concern and questions:

Enabling +5V before +3.3V-enable causes to float around 0.5V to 1.6V by +5V leaking on the 3.3V line thru any circuit in i.MX 6.

#Do the above phenomena occur in i.MX 6?

#Should +5V enable after 3.3V-enable?

  • Hi, 

      I've accepted your friendship request, and I'm still waiting for your figures and schematics to send me through Email attachment.  

  • Hi,

    I have sent e-mail to you last 26.

    Have you recieved it yet?

    *****************************************************************************

    From: Kunou Tadashi
    Sent: Wednesday, February 26, 2020 11:21 AM
    To: 'pyi@ti.com.' <pyi@ti.com.>
    Subject: RE: TI E2E support forums - Friendship request: 8412

     

    Hello, Phil san

     

    Thank you for your support.

    Please see the attached file.

     

    If you have any questions, please let me know.

     

    Best regards

    Tadashi Kunou, Panasonic

     ***************************************************************************************

    *

  • Hi,

    I'm sorry for late, because I mistook your e-mail

    T.Kuno

  • Hi, Kuno-san,

      what's the exact part number or orderable part number of PMIC? 

  • Hi, Kuno-san,

      What's the exact part number or orderable part number of PMIC? 

  • Kunou,

    I will summarize my explanation via email to close this question on e2e.

    For the i.MX 6Quad, the USB_H1_VBUS and USB_OTG_VBUS supplies recommended to have an input voltage between 4.4V and 5.25V

    The i.MX 6Quad datasheet says there are no sequencing requirements for USB_H1_VBUS and USB_OTG_VBUS and they can be powered on at any time.

     But you are indicating that this may not be true. In the PF0100 power supply, SWBST is a 600-mA boost converter that generates 5.0V-5.15V from the input voltage to provide power to USB_H1_VBUS and USB_OTG_VBUS.

     

    The problem we see with most NXP PMICs is that this input voltage range is VIN = 2.8 - 4.5 V and does not allow a 5.0V system-wide power supply.

     

    The TPS659114 solution for powering NXP i.MX 6Quad assumes that the input voltage is 5.0V (named V5IN) and does not even show the USB_H1_VBUS and USB_OTG_VBUS supplies in the diagram. If you were using this solution, 5.0V would be applied directly from V5IN to USB_H1_VBUS and USB_OTG_VBUS. If the processor cannot allow USB_xx_VBUS to be applied before NVCC_xxxx (3.3V), then you would need to add external load switch to this system.

     

    We have another solution for NXP i.MX 6DualLite, 6Solo processors which integrates a load switch:

    Powering the NXP i.MX 6Solo, 6DualLite with the TPS6521815 PMIC

    In this solution using TPS6521815 PMIC, LS2 does not turn on automatically. The load switch prevents 5V from VSYS being applied directly to USB_H1_VBUS and USB_OTG_VBUS inputs until the load switch is enabled by I2C.

    Based on NXP datasheet, both of our proposed PMIC solutions will work. We do not have any indication from other customers that there are issues with our power sequencing.