PROCESSOR-SDK-DRA7X: Multiprocessor debugging under Linux embedded

Gerardo Artola Pola1

Part Number: PROCESSOR-SDK-DRA7X
Other Parts Discussed in Thread: SYSBIOS

Hi all,

I am trying to attach a JTAG to a DSP while running embedded Linux in the CA15. Apparently there is a conflict between the CA15 and the JTAG, so it won't attach (JTAG is working OK bare metal).

The details of the HW and SW are:

Target board: DRA7x EVM

JTAG: Lauterbach Power Debug Pro

OS: Arago (Processor SDK 06.01.00.08)

kernel: 4.19.59

Any hint regarding this issue? Is module remoteproc conflicting the JTAG connection? If this is the case, is there any configuration/setting that can allow to connect to the DSP for debugging?

Thanks in advance,

over 3 years ago

0 Yordan Kamenov over 3 years ago

TI__Mastermind 42515 points

Hi Gerardo,

can you check this users guide and see if it helps:

Regards,

Yordan

0 Gerardo Artola Pola1 over 3 years ago in reply to Yordan Kamenov

Prodigy 70 points

Hi Yordan,

we are not using CCS for the moment. This is Lauterbach JTAG with own debugger software (equivalent to CSS).

I want to highlight also that we run embedded linux in the CA15. And the JTAG must be "Linux aware". Lauterbach JTAG is Linux aware, but although I can debug anything in the CA15 (inlcuding kernel level modules) I cannot attach the debugger at the same time to the DSPs. we can do this in bare metal, this is why I assume the CA15 is "interfering" the JTAG, and quite likely is the module "remoteproc" the responsible.

If you need any other info from our setup, please let us know.

BR,

0 Richard Woodruff over 3 years ago in reply to Gerardo Artola Pola1

TI__Genius 17575 points

Hello Gerardo,

It is possible to debug the DRA7xx cores one at a time or concurrently using TRACE32 for both bare metal and end-hlos+rtos use cases. A multicore end application debug often requires some awareness about the system's state. This is needed regardless of if CCS or TRACE32 is used.

If what you need to debug in the DSP flow is later in time you can always just launch a standalone TRACE32 DSP PowerView instance and do a simple 'system.attach' instead of a system.up. From here it's possible to halt/step and get DSP trace using the same techniques you would use on the ARM core.

If you need to debug the DSP boot code its a bit more involved as Linux will be writing to the prcm (power, clock, reset) aspects and this will conflict with any bare metal CMM/GEL file which you might be using with bare metal. To debug this some code changes (or targeted image specific break points) would be needed on the ARM and DSP side. Perhaps the most familiar thing to do would be just to add some looping code early in the DSP startup which allows a clean attach point. You can then advance the PC to clean spot and continue debugging. The DSP assembly harder to deal with than ARM's given instruction bundling being VLIW but it would be possible. I am not a DSP expert to give step-by-step instructions here but it can be done.

If you need to concurrent debug of the DSP and Linux that is also possible. Again, attaching to a running system is somewhat straight forward with simple CMMs which just attach and setup OS awareness and symbols. I have used this often to find longer run aborts and hangs. Debugging from the raw boot has other complications. TRACE32 provides multicore synchronized start/stop using the "Sync" command.

* Since what you are asking is very Lauterbach/TRACE32 specific you should contact Lauterbach's support. They are deep experts in this usage and have Engineers who can help you in the tool configuration for the more complex tool setups. I often get help from them if I find something is not working as expected for all the cores on DRA7xx.

Something like this might be all you need for a simple debug with a single instance where you just launch t32m6000 and run a script like:

system.cpu dra7xxdsp1
system.config.adtf TYPE ADTF2 ; fix for older T32 installs
system.option dualport on
trace.method onchip

; SYSBIOS awareness
task.config C:\T32\demo\tms320c64xx\kernel\sysbios\sysbios.t32
menu.reprogram C:\T32\demo\tms320c64xx\kernel\sysbios\sysbios.men
HELP.FILTER.Add rtossysbios
TASK.STacK.PATtern 0xbe ; stack fill pattern

; Vision SDK Sources
symbol.sourcepath.setrecursedir f:\VISION_SDK_02_07_00_00\ti_components\os_tools\bios_6_41_04_54\packages\ti\sysbios\family\arm\ducati
symbol.sourcepath.setrecursedir + f:\VISION_SDK_02_07_00_00\vision_sdk\src
symbol.sourcepath.setrecursedir + f:\VISION_SDK_02_07_00_00\ti_components
; data.load.elf f:\VISION_SDK_02_07_00_00\vision_sdk\binaries\vision_sdk\bin\tda3xx-evm\vision_sdk_c66xdsp_1_debug.xe66 /nocode /plusvm
data.load.elf d:\dra7-dsp1-fw.xe66 /nocode /plusvm
symbol.sourcepath.list

; Per
per.reprogram ~~/perdra7xxdsp.per ; some extras in here

sys.attach

break

Regards,

Richard W.

0 Gerardo Artola Pola1 over 3 years ago in reply to Richard Woodruff

Prodigy 70 points

Hi Richard,

I tried exactly that reference script you shared, with the path adjusted to my filesystem and the JTAG fails in the command "break".

I am getting always the same error. Trace32 error is "debug port fail".

To clarify my failing debug session, this are steps followed:

1) Linux is running in the CA15

2) I Open ONE Trace32 instance, using your script adjusted with local paths, and running the .cmm step by step

3) I add a status window in Trace32 "targetsystem.state"

4) Core state shows "running (boot loading active)" after "sys.attach" and before "break"

5) Debugger fails. Core status is "system down" after break command execution. Error message is "debug port fail"

Any hint?

BR,

Gerardo

0 Richard Woodruff over 3 years ago in reply to Gerardo Artola Pola1

TI__Genius 17575 points

Hello Gerardo,

"Debug port fail" tends to happen with poor signaling. For that, I try and use the best adaptor available. You could try slowing down the JTAG clock "system.JtagClock CTCK 1.mhz". Also doing things that help defeat any effects of board noise on key rails can help. One relatively simple thing would be to boost the voltage of all the VDD domains by 100mV. The easiest way to do that is to stop at the u-boot problem and send some i2c commands to the pmic.

Given the "sys.attach" worked at least part of the route (debugger to TAP) is probably good enough. If Linux hasn't brought up the DSP fully yet (power domain still down) or the like you might also get some kind of failure from TAP to DSP. There are some ways to force clocks/voltage directly through the PRCM or through the debug tap. As I mentioned before, if you can ensure your DSP is running and attach while it's in a spin loop, it may simplify this.

What build date of TRACE32 are you using? There have been incremental fixes over time for C6x. I have a build from a couple of weeks back and it worked fine on C6x on my EVM in a similar scenario with Linux.

What version of Linux is in use? There is some chance that run-time pm has shut down clocks or misconfigured some interface and that is torpedoing the communication path. I recall boot loaders versions a long time back which turned DSP clocks in an unsafe way and that resulted in the DSP booting into a weirdly crashed state. The Linux driver for loading would have to run a DSP reset sequence before loading code. From the sounds of it... it does seem like you are trying to connect before something is really running or it's stuck in some kind of odd state. How it got to this odd state would be the question {bad voltage, bad signal quality, bad clock setup, bug in older tool version, ...}. If it is working for you at bare metal it seems like chances are the full run time setup is messing some HW or SW aspect up... Do you see the same thing on the TI EVM or just your custom board? I have used concurrent debug with Linux+RTOS and have got good results, so I'm optimistic that the path will work out.

Regards,

Richard W.

0 Gerardo Artola Pola1 over 3 years ago in reply to Richard Woodruff

Prodigy 70 points

Hi Richard,

I lowered the JTAG frequency and did not help.

Also, regarding board noise, I can run AMP multiprocessor debugging examples available in Trace32 software package (in <T32_installation_dir>/demo/arm/hardware/tda2x/vayu_evm). They are baremetal examples.

This examples run to completion without errors and for all the processors. So I am assuming the JTAG, the SOC and the connection are OK.

I am using Ti EVM board. No custom board. I can forward you latter EVM details if you need.

Trace32 details are:

Vers.Software2: TRACE32 for C6000
              |    Release Sep 2019 (64-bit)
              |    Software Version: R.2019.09.000114442
              |    Build: 112182--114442.

Regarding Linux:

I am generating it with help of arago framework. Generator is <arago_SDK_dir>/configs/processor-sdk/processor-sdk-06.01.00.08-config.txt

Generated Linux version would be then

# uname -a

Linux dra7xx-evm 4.19.59-g5f8c1c6121 #1 SMP PREEMPT Wed Dec 18 03:09:55 UTC 2019 armv7l GNU/Linux

Before launching Trace32, I always boot the board and wait until I can login. I run dmesg also to check boot was OK. As an example of dmesg for the DSP1, I get

# dmesg | grep remoteproc2
[ 102.951574] remoteproc remoteproc2: 40800000.dsp is available
[ 105.288977] remoteproc remoteproc2: powering up 40800000.dsp
[ 105.315488] remoteproc remoteproc2: Booting fw image dra7-dsp1-fw.xe66, size 19618956
[ 105.481180] remoteproc remoteproc2: registered virtio2 (type 7)
[ 105.505412] remoteproc remoteproc2: remote processor 40800000.dsp is now up

Firmware loaded is generated too by arago (opencl monitor example). Is the default FW generated for booting (maybe DSP firmware is going into idle mode. Can this affect the JTAG?)

You mentioned there is a way to force clocks/voltages through PRCM registers. Actually, this is what I wanted to try, but I am not able to do. Basically, my goal would be:

Boot CA15 Linux without remoteproc
After booting set PRCM register accordingly to have the DSPs available for loading and debugging

Is this possible at all? Can you share a .cmm example of PRCM settings?

Even a gel file can work (I can convert it to .cmm).

Ideally, I would like to have at least 2 instances of Trace32 (in CA15 and DSPx), but I would be happy to have one instance of Trace32 in one DSP and gdb in the CA15 (for user space debugging).

BR,

0 Richard Woodruff over 3 years ago in reply to Gerardo Artola Pola1

TI__Genius 17575 points

Hello Gerardo,

Did you try and boost the voltage also? In your environment probably it is easiest to just use omapconf at the shell. You can compile then and add it to your filesystem (if it is not already there): https://github.com/omapconf/omapconf then at run time before trying to attach use the "set volt command" for each domain, eg: "omapconf set volt mpu 1.2". The main domains to boost before trying are 'dspeve' and 'core'.

I've not tried your exact setup to know what issue is there. The last image I would have used A15+DSP with TRAC32 was Android-based. I didn't do anything special for my local usage. I don't have the pieces in place to replicate your exact environment and I don't know that there is a way to get them shared.

If you open the per file and expand the PRCM registers (except for INSTR_PRM and CM_CORE_AON__INSTR ) and DSP ones and send I can see if some obvious state is messed up. If you expand all and the base clock for the INSTR_x is not enabled some of the internal spaces will collapse and not all the needed registers will be visible.

The idle instruction would only play a role if the SW had linked up some of the power down features to its execution. This could be seen in the PRCM registers. If that were the case, it can be defeated with a 'poke' (assuming that version of the SW is not constantly re-writing it).

Regards,

Richard W.

0 Gerardo Artola Pola1 over 3 years ago in reply to Richard Woodruff

Prodigy 70 points

Hi Richard,

I tried setting voltage for core and dspeve domains, but I am still getting debug port fail error.

I made different dumps of registers from omapconf that you can find attached. Maybe you can take a quick look and try to spot a wrong state.

Those registers are after a "fresh" boot. The software is the default generated by Arago. So far, we did not upload any custom SW.

Maybe you can spot the error, because in my case did not work so far.

BTW, I was trying to import the registers to the Clock Tree Toll to try to find any meaningful info.

Thank you in advance,

Gerardo

omapconf_export_ctt.txt

# ./omapconf export ctt
OMAPCONF (rev v1.73 built Mon Dec 23 13:52:07 UTC 2019)

HW Platform:
  Generic DRA74X (Flattened Device Tree)
  DRA75X ES2.0 GP Device (STANDARD performance (1.0GHz))
  TPS659038  ES2.2 

SW Build Details:
  Build:
    Version:  _____                    _____           _         _   
  Kernel:
    Version: 4.19.59-g5f8c1c6121
    Author: oe-user@oe-host
    Toolchain: gcc version 8.3.0 (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)
    Type: #1 SMP PREEMPT
    Date: Wed Dec 18 03:09:55 UTC 2019

The Clock Tree Tool can import register settings from a *.rd1 file.
The format of the *.rd1 file is:

DeviceName DRA75X_SR2.0
<register address> <register value>
<register address> <register value>
...

Copy the below output between the begin and end separators into a
file with the extension *.rd1 and this file can be read by the
Clock Tree Tool

|--------------------------- ctt dump begin ----------------------|
DeviceName DRA75X_SR2.0
0x4A005100 0x00000110
0x4A005120 0x00000007
0x4A00512C 0x00010A04
0x4A005130 0x00000002
0x4A00513C 0x00000204
0x4A005140 0x0000023E
0x4A005144 0x00000005
0x4A005154 0x00000205
0x4A005158 0x00000204
0x4A00515C 0x00000006
0x4A005160 0x00000007
0x4A00516C 0x00C04B00
0x4A005170 0x00000201
0x4A00519C 0x00000000
0x4A0051A0 0x00000007
0x4A0051AC 0x00010A04
0x4A0051B0 0x00000002
0x4A0051DC 0x00000000
0x4A0051E0 0x00000007
0x4A0051EC 0x00800800
0x4A0051F0 0x00000A01
0x4A0051F4 0x00000001
0x4A005210 0x00000007
0x4A00521C 0x00010A04
0x4A005220 0x00000202
0x4A005228 0x00000208
0x4A005234 0x00000007
0x4A005240 0x00004B01
0x4A005244 0x00000001
0x4A005248 0x00000003
0x4A005254 0x00000000
0x4A005284 0x00000005
0x4A005290 0x00000000
0x4A005294 0x00000001
0x4A0052A4 0x00000000
0x4A0052A8 0x00000007
0x4A0052B4 0x0000FA04
0x4A0052B8 0x00000204
0x4A0052C0 0x00000228
0x4A0052C4 0x00000208
0x4A0052D8 0x00000007
0x4A0052E4 0x00010A04
0x4A0052E8 0x00000002
0x4A005420 0x00070000
0x4A005520 0x01000001
0x4A005550 0x00030000
0x4A005558 0x00030000
0x4A005560 0x00030000
0x4A005568 0x00000002
0x4A005570 0x00000002
0x4A005578 0x00030000
0x4A005580 0x00030000
0x4A005620 0x00070000
0x4A005660 0x00070000
0x4A0056A0 0x00070000
0x4A005744 0x00020002
0x4A005764 0x00000001
0x4A008140 0x00000007
0x4A00814C 0x00006004
0x4A008150 0x00000804
0x4A008158 0x00000003
0x4A00815C 0x00000004
0x4A008160 0x0000000A
0x4A008164 0x00000002
0x4A008180 0x00000007
0x4A00818C 0x0401E009
0x4A008190 0x00000202
0x4A008200 0x00000007
0x4A00820C 0x04004B00
0x4A008210 0x0000040F
0x4A00821C 0x00000101
0x4A008728 0x00030000
0x4A008778 0x00000001
0x4A008780 0x00000001
0x4A008920 0x00070000
0x4A008B30 0x00000001
0x4A008B38 0x00000001
0x4A008B40 0x00000000
0x4A008C00 0x04030000
0x4A008E20 0x00030000
0x4A008E28 0x00030000
0x4A008E40 0x00030000
0x4A008E50 0x01000001
0x4A008F20 0x00060001
0x4A008F28 0x00020001
0x4A009020 0x00000001
0x4A009028 0x00070000
0x4A009030 0x00070000
0x4A009120 0x00070000
0x4A009130 0x00070000
0x4A009220 0x0A070000
0x4A009328 0x01040002
0x4A009330 0x01040002
0x4A009340 0x00000101
0x4A009348 0x00070000
0x4A009350 0x00070000
0x4A009358 0x00070000
0x4A009388 0x00000102
0x4A0093B0 0x00000702
0x4A0093B8 0x00070000
0x4A0093D0 0x08000002
0x4A0093E0 0x00000001
0x4A0093E8 0x00000001
0x4A0093F0 0x00040101
0x4A009620 0x00030000
0x4A009728 0x00030000
0x4A009730 0x00020002
0x4A009738 0x00030000
0x4A009740 0x00030000
0x4A009748 0x00030000
0x4A009750 0x00030000
0x4A009760 0x00030000
0x4A009768 0x00030000
0x4A009770 0x00030000
0x4A009778 0x00020001
0x4A009780 0x00020001
0x4A009788 0x00030000
0x4A009790 0x00030000
0x4A009798 0x00030000
0x4A0097A0 0x00020002
0x4A0097A8 0x00030000
0x4A0097B0 0x00030000
0x4A0097B8 0x00030000
0x4A0097C4 0x00030000
0x4A0097C8 0x00030000
0x4A0097D0 0x00020002
0x4A0097D8 0x00030000
0x4A0097F0 0x00030000
0x4A0097F8 0x00030000
0x4A009800 0x00030000
0x4A009808 0x00030000
0x4A009810 0x00020101
0x4A009818 0x00030000
0x4A009820 0x00030000
0x4A009828 0x00020002
0x4A009830 0x07030000
0x4A009838 0x01030000
0x4A009840 0x00010002
0x4A009848 0x00010002
0x4A009850 0x00010002
0x4A009858 0x00030000
0x4A009860 0x00030000
0x4A009868 0x04030000
0x4A009870 0x00030000
0x4A009878 0x00030000
0x4A009890 0x00000002
0x4A009898 0x00030000
0x4A0098A0 0x00030000
0x4A0098A8 0x00030000
0x4A0098B0 0x00030000
0x4A0098B8 0x00030000
0x4A0098C0 0x00000001
0x4A0098C8 0x00030000
0x4A0098D0 0x00030000
0x4A0098E0 0x00030000
0x4A0098E8 0x00030000
0x4A0098F0 0x00030000
0x4A0098F8 0x00030000
0x4A009904 0x00030000
0x4A009908 0x00030000
0x4AE06108 0x00000000
0x4AE0610C 0x00000000
0x4AE06114 0x00000000
0x4AE06118 0x00000001
0x4AE06128 0x00000000
0x4AE0612C 0x00000000
0x4AE06130 0x00000000
0x4AE06134 0x00000000
0x4AE06138 0x00000000
0x4AE06144 0x00000000
0x4AE06148 0x00000000
0x4AE0614C 0x00000000
0x4AE06150 0x00000000
0x4AE06154 0x00000000
0x4AE06158 0x00000000
0x4AE06164 0x00000000
0x4AE06168 0x00000000
0x4AE0616C 0x00000000
0x4AE06170 0x00000000
0x4AE06174 0x00000000
0x4AE06178 0x00000000
0x4AE06180 0x00000000
0x4AE06184 0x00000000
0x4AE06188 0x00000000
0x4AE0618C 0x00000000
0x4AE06190 0x00000000
0x4AE06194 0x00000000
0x4AE06198 0x00000000
0x4AE0619C 0x00000000
0x4AE061A0 0x00000000
0x4AE061A4 0x00000000
0x4AE061A8 0x00000000
0x4AE061AC 0x00000000
0x4AE061B0 0x00000000
0x4AE061B4 0x00000000
0x4AE061B8 0x00000000
0x4AE061BC 0x00000000
0x4AE061C0 0x00000000
0x4AE061C8 0x00000000
0x4AE061CC 0x00000000
0x4AE061D0 0x00000000
0x4AE061D4 0x00000000
0x4AE061D8 0x00000000
0x4AE061E0 0x00000000
0x4AE07830 0x00030000
0x4AE07838 0x00030000
0x4AE07840 0x01000002
0x4AE07878 0x00030000
0x4AE07880 0x00030000
0x4AE07888 0x00030000
|---------------------------- ctt dump end -----------------------|

omapconf: powerdm_deinit(): cpu not supported!!!
omapconf: clockdm_deinit(): cpu not supported!!!

omapconf_dump_prcm_dsp.txt

# ./omapconf dump prcm dsp
OMAPCONF (rev v1.73 built Mon Dec 23 13:52:07 UTC 2019)

HW Platform:
  Generic DRA74X (Flattened Device Tree)
  DRA75X ES2.0 GP Device (STANDARD performance (1.0GHz))
  TPS659038  ES2.2 

SW Build Details:
  Build:
    Version:  _____                    _____           _         _   
  Kernel:
    Version: 4.19.59-g5f8c1c6121
    Author: oe-user@oe-host
    Toolchain: gcc version 8.3.0 (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)
    Type: #1 SMP PREEMPT
    Date: Wed Dec 18 03:09:55 UTC 2019

|--------------------------------------------------|
| PRM DSP Reg. Name    | Reg. Address | Reg. Value |
|--------------------------------------------------|
| PM_DSP1_PWRSTCTRL    | 0x4AE06400   | 0x003F0000 |
| PM_DSP1_PWRSTST      | 0x4AE06404   | 0x00000000 |
| RM_DSP1_RSTCTRL      | 0x4AE06410   | 0x00000003 |
| RM_DSP1_RSTST        | 0x4AE06414   | 0x00000003 |
| RM_DSP1_DSP1_CONTEXT | 0x4AE06424   | 0x00000701 |
| PM_DSP2_PWRSTCTRL    | 0x4AE07B00   | 0x003F0000 |
| PM_DSP2_PWRSTST      | 0x4AE07B04   | 0x00000000 |
| RM_DSP2_RSTCTRL      | 0x4AE07B10   | 0x00000003 |
| RM_DSP2_RSTST        | 0x4AE07B14   | 0x0000000B |
| RM_DSP2_DSP2_CONTEXT | 0x4AE07B24   | 0x00000701 |
|--------------------------------------------------|

|-------------------------------------------------------|
| CM CORE AON DSP Reg. Name | Reg. Address | Reg. Value |
|-------------------------------------------------------|
| CM_DSP1_CLKSTCTRL         | 0x4A005400   | 0x00000003 |
| CM_DSP1_STATICDEP         | 0x4A005404   | 0x00000020 |
| CM_DSP1_DYNAMICDEP        | 0x4A005408   | 0x04000020 |
| CM_DSP1_DSP1_CLKCTRL      | 0x4A005420   | 0x00070000 |
| CM_DSP2_CLKSTCTRL         | 0x4A005600   | 0x00000003 |
| CM_DSP2_STATICDEP         | 0x4A005604   | 0x00000020 |
| CM_DSP2_DYNAMICDEP        | 0x4A005608   | 0x04000020 |
| CM_DSP2_DSP2_CLKCTRL      | 0x4A005620   | 0x00070000 |
|-------------------------------------------------------|

omapconf: powerdm_deinit(): cpu not supported!!!
omapconf: clockdm_deinit(): cpu not supported!!!

omapconf_dump_prcm_core.txt

# ./omapconf dump prcm core
OMAPCONF (rev v1.73 built Mon Dec 23 13:52:07 UTC 2019)

HW Platform:
  Generic DRA74X (Flattened Device Tree)
  DRA75X ES2.0 GP Device (STANDARD performance (1.0GHz))
  TPS659038  ES2.2 

SW Build Details:
  Build:
    Version:  _____                    _____           _         _   
  Kernel:
    Version: 4.19.59-g5f8c1c6121
    Author: oe-user@oe-host
    Toolchain: gcc version 8.3.0 (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)
    Type: #1 SMP PREEMPT
    Date: Wed Dec 18 03:09:55 UTC 2019

|----------------------------------------------------------------------|
| PRM CORE Reg. Name                       | Reg. Address | Reg. Value |
|----------------------------------------------------------------------|
| PM_CORE_PWRSTCTRL                        | 0x4AE06700   | 0x03FF0F07 |
| PM_CORE_PWRSTST                          | 0x4AE06704   | 0x00003FF7 |
| RM_L3MAIN1_L3_MAIN_1_CONTEXT             | 0x4AE06724   | 0x00000000 |
| RM_L3MAIN1_GPMC_CONTEXT                  | 0x4AE0672C   | 0x00000000 |
| RM_L3MAIN1_MMU_EDMA_CONTEXT              | 0x4AE06734   | 0x00000002 |
| RM_L3MAIN1_MMU_PCIESS_CONTEXT            | 0x4AE0674C   | 0x00000002 |
| PM_L3MAIN1_OCMC_RAM1_WKDEP               | 0x4AE06750   | 0x00000000 |
| RM_L3MAIN1_OCMC_RAM1_CONTEXT             | 0x4AE06754   | 0x00000101 |
| PM_L3MAIN1_OCMC_RAM2_WKDEP               | 0x4AE06758   | 0x00000000 |
| RM_L3MAIN1_OCMC_RAM2_CONTEXT             | 0x4AE0675C   | 0x00000101 |
| PM_L3MAIN1_OCMC_RAM3_WKDEP               | 0x4AE06760   | 0x00000000 |
| RM_L3MAIN1_OCMC_RAM3_CONTEXT             | 0x4AE06764   | 0x00000101 |
| RM_L3MAIN1_OCMC_ROM_CONTEXT              | 0x4AE0676C   | 0x00000101 |
| PM_L3MAIN1_TPCC_WKDEP                    | 0x4AE06770   | 0x00000000 |
| RM_L3MAIN1_TPCC_CONTEXT                  | 0x4AE06774   | 0x00000000 |
| PM_L3MAIN1_TPTC1_WKDEP                   | 0x4AE06778   | 0x00000000 |
| RM_L3MAIN1_TPTC1_CONTEXT                 | 0x4AE0677C   | 0x00000000 |
| PM_L3MAIN1_TPTC2_WKDEP                   | 0x4AE06780   | 0x00000000 |
| RM_L3MAIN1_TPTC2_CONTEXT                 | 0x4AE06784   | 0x00000000 |
| RM_L3MAIN1_VCP1_CONTEXT                  | 0x4AE0678C   | 0x00000000 |
| RM_L3MAIN1_VCP2_CONTEXT                  | 0x4AE06794   | 0x00000000 |
| RM_L3MAIN1_SPARE_CME_CONTEXT             | 0x4AE0679C   | 0x00000001 |
| RM_L3MAIN1_SPARE_HDMI_CONTEXT            | 0x4AE067A4   | 0x00000001 |
| RM_L3MAIN1_SPARE_ICM_CONTEXT             | 0x4AE067AC   | 0x00000001 |
| RM_L3MAIN1_SPARE_IVA2_CONTEXT            | 0x4AE067B4   | 0x00000001 |
| RM_L3MAIN1_SPARE_SATA2_CONTEXT           | 0x4AE067BC   | 0x00000001 |
| RM_L3MAIN1_SPARE_UNKNOWN4_CONTEXT        | 0x4AE067C4   | 0x00000001 |
| RM_L3MAIN1_SPARE_UNKNOWN5_CONTEXT        | 0x4AE067CC   | 0x00000001 |
| RM_L3MAIN1_SPARE_UNKNOWN6_CONTEXT        | 0x4AE067D4   | 0x00000001 |
| RM_L3MAIN1_SPARE_VIDEOPLL1_CONTEXT       | 0x4AE067DC   | 0x00000001 |
| RM_L3MAIN1_SPARE_VIDEOPLL2_CONTEXT       | 0x4AE067F4   | 0x00000001 |
| RM_L3MAIN1_SPARE_VIDEOPLL3_CONTEXT       | 0x4AE067FC   | 0x00000001 |
| RM_IPU2_RSTCTRL                          | 0x4AE06910   | 0x00000007 |
| RM_IPU2_RSTST                            | 0x4AE06914   | 0x00000007 |
| RM_IPU2_IPU2_CONTEXT                     | 0x4AE06924   | 0x00000003 |
| RM_DMA_DMA_SYSTEM_CONTEXT                | 0x4AE06A24   | 0x00000000 |
| RM_EMIF_DMM_CONTEXT                      | 0x4AE06B24   | 0x00000000 |
| RM_EMIF_EMIF_OCP_FW_CONTEXT              | 0x4AE06B2C   | 0x00000003 |
| RM_EMIF_EMIF1_CONTEXT                    | 0x4AE06B34   | 0x00000003 |
| RM_EMIF_EMIF2_CONTEXT                    | 0x4AE06B3C   | 0x00000003 |
| RM_EMIF_EMIF_DLL_CONTEXT                 | 0x4AE06B44   | 0x00000001 |
| RM_ATL_ATL_CONTEXT                       | 0x4AE06C24   | 0x00000000 |
| RM_L4CFG_L4_CFG_CONTEXT                  | 0x4AE06D24   | 0x00000000 |
| RM_L4CFG_SPINLOCK_CONTEXT                | 0x4AE06D2C   | 0x00000000 |
| RM_L4CFG_MAILBOX1_CONTEXT                | 0x4AE06D34   | 0x00000000 |
| RM_L4CFG_SAR_ROM_CONTEXT                 | 0x4AE06D3C   | 0x00000001 |
| RM_L4CFG_OCP2SCP2_CONTEXT                | 0x4AE06D44   | 0x00000001 |
| RM_L4CFG_MAILBOX2_CONTEXT                | 0x4AE06D4C   | 0x00000000 |
| RM_L4CFG_MAILBOX3_CONTEXT                | 0x4AE06D54   | 0x00000000 |
| RM_L4CFG_MAILBOX4_CONTEXT                | 0x4AE06D5C   | 0x00000000 |
| RM_L4CFG_MAILBOX5_CONTEXT                | 0x4AE06D64   | 0x00000000 |
| RM_L4CFG_MAILBOX6_CONTEXT                | 0x4AE06D6C   | 0x00000000 |
| RM_L4CFG_MAILBOX7_CONTEXT                | 0x4AE06D74   | 0x00000000 |
| RM_L4CFG_MAILBOX8_CONTEXT                | 0x4AE06D7C   | 0x00000000 |
| RM_L4CFG_MAILBOX9_CONTEXT                | 0x4AE06D84   | 0x00000000 |
| RM_L4CFG_MAILBOX10_CONTEXT               | 0x4AE06D8C   | 0x00000000 |
| RM_L4CFG_MAILBOX11_CONTEXT               | 0x4AE06D94   | 0x00000000 |
| RM_L4CFG_MAILBOX12_CONTEXT               | 0x4AE06D9C   | 0x00000000 |
| RM_L4CFG_MAILBOX13_CONTEXT               | 0x4AE06DA4   | 0x00000000 |
| RM_L4CFG_SPARE_SMARTREFLEX_RTC_CONTEXT   | 0x4AE06DAC   | 0x00000001 |
| RM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CONTEXT | 0x4AE06DB4   | 0x00000001 |
| RM_L4CFG_SPARE_SMARTREFLEX_WKUP_CONTEXT  | 0x4AE06DBC   | 0x00000001 |
| RM_L4CFG_IO_DELAY_BLOCK_CONTEXT          | 0x4AE06DC4   | 0x00000001 |
| RM_L3INSTR_L3_MAIN_2_CONTEXT             | 0x4AE06E24   | 0x00000000 |
| RM_L3INSTR_L3_INSTR_CONTEXT              | 0x4AE06E2C   | 0x00000000 |
| RM_L3INSTR_OCP_WP_NOC_CONTEXT            | 0x4AE06E44   | 0x00000103 |
|----------------------------------------------------------------------|

|----------------------------------------------------------------------|
| CM CORE CORE Reg. Name                   | Reg. Address | Reg. Value |
|----------------------------------------------------------------------|
| CM_L3MAIN1_CLKSTCTRL                     | 0x4A008700   | 0x00000303 |
| CM_L3MAIN1_DYNAMICDEP                    | 0x4A008708   | 0xF4F4F51F |
| CM_L3MAIN1_L3_MAIN_1_CLKCTRL             | 0x4A008720   | 0x00000001 |
| CM_L3MAIN1_GPMC_CLKCTRL                  | 0x4A008728   | 0x00030000 |
| CM_L3MAIN1_MMU_EDMA_CLKCTRL              | 0x4A008730   | 0x00000001 |
| CM_L3MAIN1_MMU_PCIESS_CLKCTRL            | 0x4A008748   | 0x00000001 |
| CM_L3MAIN1_OCMC_RAM1_CLKCTRL             | 0x4A008750   | 0x00000001 |
| CM_L3MAIN1_OCMC_RAM2_CLKCTRL             | 0x4A008758   | 0x00000001 |
| CM_L3MAIN1_OCMC_RAM3_CLKCTRL             | 0x4A008760   | 0x00000001 |
| CM_L3MAIN1_OCMC_ROM_CLKCTRL              | 0x4A008768   | 0x00000001 |
| CM_L3MAIN1_TPCC_CLKCTRL                  | 0x4A008770   | 0x00000001 |
| CM_L3MAIN1_TPTC1_CLKCTRL                 | 0x4A008778   | 0x00000001 |
| CM_L3MAIN1_TPTC2_CLKCTRL                 | 0x4A008780   | 0x00000001 |
| CM_L3MAIN1_VCP1_CLKCTRL                  | 0x4A008788   | 0x00000001 |
| CM_L3MAIN1_VCP2_CLKCTRL                  | 0x4A008790   | 0x00000001 |
| CM_L3MAIN1_SPARE_CME_CLKCTRL             | 0x4A008798   | 0x00000001 |
| CM_L3MAIN1_SPARE_HDMI_CLKCTRL            | 0x4A0087A0   | 0x00000001 |
| CM_L3MAIN1_SPARE_ICM_CLKCTRL             | 0x4A0087A8   | 0x00000001 |
| CM_L3MAIN1_SPARE_IVA2_CLKCTRL            | 0x4A0087B0   | 0x00000001 |
| CM_L3MAIN1_SPARE_SATA2_CLKCTRL           | 0x4A0087B8   | 0x00000001 |
| CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL        | 0x4A0087C0   | 0x00000001 |
| CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL        | 0x4A0087C8   | 0x00000001 |
| CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL        | 0x4A0087D0   | 0x00000001 |
| CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL       | 0x4A0087D8   | 0x00000001 |
| CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL       | 0x4A0087F0   | 0x00000001 |
| CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL       | 0x4A0087F8   | 0x00000001 |
| CM_IPU2_CLKSTCTRL                        | 0x4A008900   | 0x00000003 |
| CM_IPU2_STATICDEP                        | 0x4A008904   | 0x00000000 |
| CM_IPU2_DYNAMICDEP                       | 0x4A008908   | 0x04000020 |
| CM_IPU2_IPU2_CLKCTRL                     | 0x4A008920   | 0x00070000 |
| CM_DMA_CLKSTCTRL                         | 0x4A008A00   | 0x00000103 |
| CM_DMA_STATICDEP                         | 0x4A008A04   | 0x00000020 |
| CM_DMA_DYNAMICDEP                        | 0x4A008A08   | 0x00000000 |
| CM_DMA_DMA_SYSTEM_CLKCTRL                | 0x4A008A20   | 0x00000001 |
| CM_EMIF_CLKSTCTRL                        | 0x4A008B00   | 0x00000703 |
| CM_EMIF_DMM_CLKCTRL                      | 0x4A008B20   | 0x00000001 |
| CM_EMIF_EMIF_OCP_FW_CLKCTRL              | 0x4A008B28   | 0x00000001 |
| CM_EMIF_EMIF1_CLKCTRL                    | 0x4A008B30   | 0x00000001 |
| CM_EMIF_EMIF2_CLKCTRL                    | 0x4A008B38   | 0x00000001 |
| CM_EMIF_EMIF_DLL_CLKCTRL                 | 0x4A008B40   | 0x00000000 |
| CM_ATL_ATL_CLKCTRL                       | 0x4A008C00   | 0x04030000 |
| CM_ATL_CLKSTCTRL                         | 0x4A008C20   | 0x00000003 |
| CM_L4CFG_CLKSTCTRL                       | 0x4A008D00   | 0x00000303 |
| CM_L4CFG_DYNAMICDEP                      | 0x4A008D08   | 0x040B08B0 |
| CM_L4CFG_L4_CFG_CLKCTRL                  | 0x4A008D20   | 0x00000001 |
| CM_L4CFG_SPINLOCK_CLKCTRL                | 0x4A008D28   | 0x00000001 |
| CM_L4CFG_MAILBOX1_CLKCTRL                | 0x4A008D30   | 0x00000001 |
| CM_L4CFG_SAR_ROM_CLKCTRL                 | 0x4A008D38   | 0x00000001 |
| CM_L4CFG_OCP2SCP2_CLKCTRL                | 0x4A008D40   | 0x00000001 |
| CM_L4CFG_MAILBOX2_CLKCTRL                | 0x4A008D48   | 0x00000001 |
| CM_L4CFG_MAILBOX3_CLKCTRL                | 0x4A008D50   | 0x00000001 |
| CM_L4CFG_MAILBOX4_CLKCTRL                | 0x4A008D58   | 0x00000001 |
| CM_L4CFG_MAILBOX5_CLKCTRL                | 0x4A008D60   | 0x00000001 |
| CM_L4CFG_MAILBOX6_CLKCTRL                | 0x4A008D68   | 0x00000001 |
| CM_L4CFG_MAILBOX7_CLKCTRL                | 0x4A008D70   | 0x00000001 |
| CM_L4CFG_MAILBOX8_CLKCTRL                | 0x4A008D78   | 0x00000001 |
| CM_L4CFG_MAILBOX9_CLKCTRL                | 0x4A008D80   | 0x00000001 |
| CM_L4CFG_MAILBOX10_CLKCTRL               | 0x4A008D88   | 0x00000001 |
| CM_L4CFG_MAILBOX11_CLKCTRL               | 0x4A008D90   | 0x00000001 |
| CM_L4CFG_MAILBOX12_CLKCTRL               | 0x4A008D98   | 0x00000001 |
| CM_L4CFG_MAILBOX13_CLKCTRL               | 0x4A008DA0   | 0x00000001 |
| CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL   | 0x4A008DA8   | 0x00000001 |
| CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL | 0x4A008DB0   | 0x00000001 |
| CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL  | 0x4A008DB8   | 0x00000001 |
| CM_L4CFG_IO_DELAY_BLOCK_CLKCTRL          | 0x4A008DC0   | 0x00000001 |
| CM_L3INSTR_CLKSTCTRL                     | 0x4A008E00   | 0x00000603 |
| CM_L3INSTR_L3_MAIN_2_CLKCTRL             | 0x4A008E20   | 0x00030000 |
| CM_L3INSTR_L3_INSTR_CLKCTRL              | 0x4A008E28   | 0x00030000 |
| CM_L3INSTR_OCP_WP_NOC_CLKCTRL            | 0x4A008E40   | 0x00030000 |
| CM_L3INSTR_DLL_AGING_CLKCTRL             | 0x4A008E48   | 0x00000001 |
| CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL   | 0x4A008E50   | 0x01000001 |
|----------------------------------------------------------------------|

|----------------------------------------------------------------------|
| CM CORE AON RESTORE Reg. Name            | Reg. Address | Reg. Value |
|----------------------------------------------------------------------|
| CM_CLKSEL_CORE_RESTORE                   | 0x4A005E00   | 0x00000110 |
| CM_DIV_M2_DPLL_CORE_RESTORE              | 0x4A005E04   | 0x00000002 |
| CM_DIV_M3_DPLL_CORE_RESTORE              | 0x4A005E08   | 0x00000001 |
| CM_DIV_H11_DPLL_CORE_RESTORE             | 0x4A005E0C   | 0x00000001 |
| CM_DIV_H12_DPLL_CORE_RESTORE             | 0x4A005E10   | 0x00000204 |
| CM_DIV_H13_DPLL_CORE_RESTORE             | 0x4A005E14   | 0x0000023E |
| CM_DIV_H14_DPLL_CORE_RESTORE             | 0x4A005E18   | 0x00000005 |
| CM_DIV_H21_DPLL_CORE_RESTORE             | 0x4A005E1C   | 0x00000001 |
| CM_DIV_H22_DPLL_CORE_RESTORE             | 0x4A005E20   | 0x00000205 |
| CM_DIV_H23_DPLL_CORE_RESTORE             | 0x4A005E24   | 0x00000204 |
| CM_DIV_H24_DPLL_CORE_RESTORE             | 0x4A005E28   | 0x00000006 |
| CM_CLKSEL_DPLL_CORE_RESTORE              | 0x4A005E2C   | 0x00010A04 |
| CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE      | 0x4A005E30   | 0x00000000 |
| CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE      | 0x4A005E34   | 0x00000000 |
| CM_CLKMODE_DPLL_CORE_RESTORE             | 0x4A005E38   | 0x00000007 |
| CM_SHADOW_FREQ_CONFIG2_RESTORE           | 0x4A005E3C   | 0x00000004 |
| CM_SHADOW_FREQ_CONFIG1_RESTORE           | 0x4A005E40   | 0x0005080C |
| CM_AUTOIDLE_DPLL_CORE_RESTORE            | 0x4A005E44   | 0x00000001 |
| CM_MPU_CLKSTCTRL_RESTORE                 | 0x4A005E48   | 0x00000103 |
| CM_CM_CORE_AON_PROFILING_CLKCTRL_RESTORE | 0x4A005E4C   | 0x00030000 |
| CM_DYN_DEP_PRESCAL_RESTORE               | 0x4A005E50   | 0x00000020 |
|----------------------------------------------------------------------|

|-------------------------------------------------------------------|
| CM CORE RESTORE Reg. Name             | Reg. Address | Reg. Value |
|-------------------------------------------------------------------|
| CM_L3MAIN1_CLKSTCTRL_RESTORE          | 0x4A009E18   | 0x00000303 |
| CM_L4CFG_CLKSTCTRL_RESTORE            | 0x4A009E20   | 0x00000303 |
| CM_L4PER_CLKSTCTRL_RESTORE            | 0x4A009E28   | 0x01A38503 |
| CM_L3INIT_CLKSTCTRL_RESTORE           | 0x4A009E2C   | 0x01718F02 |
| CM_L3INSTR_L3_MAIN_2_CLKCTRL_RESTORE  | 0x4A009E30   | 0x00030000 |
| CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE   | 0x4A009E34   | 0x00030000 |
| CM_L3INSTR_OCP_WP_NOC_CLKCTRL_RESTORE | 0x4A009E38   | 0x00030000 |
| CM_CM_CORE_PROFILING_CLKCTRL_RESTORE  | 0x4A009E3C   | 0x00030000 |
| CM_L3MAIN1_DYNAMICDEP_RESTORE         | 0x4A009E48   | 0xF4F4F51F |
| CM_L4CFG_DYNAMICDEP_RESTORE           | 0x4A009E58   | 0x040B08B0 |
| CM_L4PER_DYNAMICDEP_RESTORE           | 0x4A009E5C   | 0x04004188 |
| CM_COREAON_IO_SRCOMP_CLKCTRL_RESTORE  | 0x4A009E60   | 0x00000000 |
| CM_DMA_STATICDEP_RESTORE              | 0x4A009E6C   | 0x00000020 |
|-------------------------------------------------------------------|

omapconf: powerdm_deinit(): cpu not supported!!!
omapconf: clockdm_deinit(): cpu not supported!!!

omapconf_dump_prcm.txt

omapconf_dump_dpll_dsp.txt

# ./omapconf dump dpll dsp
OMAPCONF (rev v1.73 built Mon Dec 23 13:52:07 UTC 2019)

HW Platform:
  Generic DRA74X (Flattened Device Tree)
  DRA75X ES2.0 GP Device (STANDARD performance (1.0GHz))
  TPS659038  ES2.2 

SW Build Details:
  Build:
    Version:  _____                    _____           _         _   
  Kernel:
    Version: 4.19.59-g5f8c1c6121
    Author: oe-user@oe-host
    Toolchain: gcc version 8.3.0 (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)
    Type: #1 SMP PREEMPT
    Date: Wed Dec 18 03:09:55 UTC 2019

|--------------------------------------------------------|
| DPLL_DSP Reg. Name         | Reg. Address | Reg. Value |
|--------------------------------------------------------|
| CM_CLKMODE_DPLL_DSP        | 0x4A005234   | 0x00000007 |
| CM_IDLEST_DPLL_DSP         | 0x4A005238   | 0x00000012 |
| CM_AUTOIDLE_DPLL_DSP       | 0x4A00523C   | 0x00000001 |
| CM_CLKSEL_DPLL_DSP         | 0x4A005240   | 0x00004B01 |
| CM_BYPCLK_DPLL_DSP         | 0x4A005254   | 0x00000000 |
| CM_DIV_M2_DPLL_DSP         | 0x4A005244   | 0x00000001 |
| CM_DIV_M3_DPLL_DSP         | 0x4A005248   | 0x00000003 |
| CM_SSC_DELTAMSTEP_DPLL_DSP | 0x4A00524C   | 0x00000000 |
| CM_SSC_MODFREQDIV_DPLL_DSP | 0x4A005250   | 0x00000000 |
|--------------------------------------------------------|

omapconf: powerdm_deinit(): cpu not supported!!!
omapconf: clockdm_deinit(): cpu not supported!!!

omapconf_dump_dpll_core.txt

# ./omapconf dump dpll core
OMAPCONF (rev v1.73 built Mon Dec 23 13:52:07 UTC 2019)

HW Platform:
  Generic DRA74X (Flattened Device Tree)
  DRA75X ES2.0 GP Device (STANDARD performance (1.0GHz))
  TPS659038  ES2.2 

SW Build Details:
  Build:
    Version:  _____                    _____           _         _   
  Kernel:
    Version: 4.19.59-g5f8c1c6121
    Author: oe-user@oe-host
    Toolchain: gcc version 8.3.0 (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)
    Type: #1 SMP PREEMPT
    Date: Wed Dec 18 03:09:55 UTC 2019

|---------------------------------------------------------|
| DPLL_CORE Reg. Name         | Reg. Address | Reg. Value |
|---------------------------------------------------------|
| CM_CLKMODE_DPLL_CORE        | 0x4A005120   | 0x00000007 |
| CM_IDLEST_DPLL_CORE         | 0x4A005124   | 0x0000001F |
| CM_AUTOIDLE_DPLL_CORE       | 0x4A005128   | 0x00000001 |
| CM_CLKSEL_DPLL_CORE         | 0x4A00512C   | 0x00010A04 |
| CM_DIV_M2_DPLL_CORE         | 0x4A005130   | 0x00000002 |
| CM_DIV_M3_DPLL_CORE         | 0x4A005134   | 0x00000001 |
| CM_SSC_DELTAMSTEP_DPLL_CORE | 0x4A005148   | 0x00000000 |
| CM_SSC_MODFREQDIV_DPLL_CORE | 0x4A00514C   | 0x00000000 |
| CM_DIV_H11_DPLL_CORE        | 0x4A005138   | 0x00000001 |
| CM_DIV_H12_DPLL_CORE        | 0x4A00513C   | 0x00000204 |
| CM_DIV_H13_DPLL_CORE        | 0x4A005140   | 0x0000023E |
| CM_DIV_H14_DPLL_CORE        | 0x4A005144   | 0x00000005 |
| CM_DIV_H21_DPLL_CORE        | 0x4A005150   | 0x00000001 |
| CM_DIV_H22_DPLL_CORE        | 0x4A005154   | 0x00000205 |
| CM_DIV_H23_DPLL_CORE        | 0x4A005158   | 0x00000204 |
| CM_DIV_H24_DPLL_CORE        | 0x4A00515C   | 0x00000006 |
|---------------------------------------------------------|

omapconf: powerdm_deinit(): cpu not supported!!!
omapconf: clockdm_deinit(): cpu not supported!!!

0 Richard Woodruff over 3 years ago in reply to Gerardo Artola Pola1

TI__Genius 17575 points

Hello Gerardo.

I was expecting to get the extracting using the TRACE32 per file save and not from omapconf. Never the less I was able to merge and re-load it into the TRACE32 simulator for full decoding.

From what I see it looks like DSP2 is completely OFF and DSP1 is mostly powered+clocked/off and in reset at this time. The EMU domain also seems to be INACTIVE. It will not be possible take debug control of the DSP and do anything at this point. If the power domains should be set to on,then the clock domain moved to sw_wake, then the modulemode enabled, then resets can be removed. Whenever the register snapshot was taken the DSP was not really up. I suppose it's possible something was printed on the UART which said it might be but that is not what the register dump shows.

I've attached a marked-up register decode of what to look at. I've also attached the cmm I used. The attached picture shows an easy way to generate it from addr, value pairs.

I'm not sure if the dsp test already ran and exited or never was launched. But its not in a state to debug. As I mention if you can attach while its running or force the state of the highlighted registers (without the SW undoing it) jtag based debug control is possible.

/cfs-file/__key/communityserver-discussions-components-files/791/dra7xx_5F00_dsp1_5F00_dsp2_5F00_decode.pdf

/cfs-file/__key/communityserver-discussions-components-files/791/simload.cmm

Regards,

Richard W.

0 Gerardo Artola Pola1 over 3 years ago in reply to Richard Woodruff

Prodigy 70 points

Hi Richard,

sorry for the wrong format of the registers data, but quick question, what is exactly the "TRACE32 per file save"?

Do you run a per.view command? But if this is the way to get the register dump, I cannot execute "break" command. Is there another way to get this registers from Trace32, without "break"?

Please clarify how I can get the register dump to facilitate your import.

Would it be possible to boot Linux without remoteproc (no DSP FW loaded) and run a .cmm sequence of PRCM instructions to wake up the dsp's (Without trashing Linux in the CA15)?

I am now inspecting the DSP firrmware loaded at boot time. If there is no more option than using remotproc, will try at least to leave the DSP firmware in an endless loop.
Maybe the DSP will stay ON for the rest of the debugging session.

BR,

0 Richard Woodruff over 3 years ago in reply to Gerardo Artola Pola1

TI__Genius 17575 points

Hello Gerardo,

-0-

What I mean by per file extraction can be seen in this video. It is possible to get all local PRCM registers by halting the A15 or by just attaching and using the /dualport option. Do not open the INSTR regions unless their clock is on. The Local MPU registers only are visible from the A15 while in break. The copy all to clipboard or print to a file saves all the registers. There are also a 'store' and 'clipstore' commands.

/cfs-file/__key/communityserver-discussions-components-files/791/lb_5F00_per_5F00_2020_2D00_06_2D00_02_5F00_14h50_5F00_05.mp4

-1-

I tried to attach to DSP while Linux was running on my A15. If the DSP is in reset I can see the states as you mention. If I manually sequence the DSP up as per the TRM I am to break and use the debugger. The sequence is (power domain on, module on, remove rst_dsp1, load up some code so it doesn't crash on start, release reset DSP1_LRST). I made a short video.

/cfs-file/__key/communityserver-discussions-components-files/791/attach_5F00_dsp1_5F00_linux_5F00_2020_2D00_06_2D00_02_5F00_14h47_5F00_21.7z

-2-

As I've indicated. Some coordination needs to happen to ensure a good attach point. Once you are attached normal debugging can happen unless the master resets the debugger.

Regards,

Richard W.

0 Richard Woodruff over 3 years ago in reply to Richard Woodruff

TI__Genius 17575 points

BTW, I made a simple script which does what the video shows. To debug an attach point to the dsp needs to be identified in your code. You could compile that in or you could use the debugger to patch on the fly to work. I find for code where I have full control often a rebuild is better, when its code which is out of my control, some run time debugger assisted patching will work. The run time patching often requires experience with the assembly language.

/cfs-file/__key/communityserver-discussions-components-files/791/8562.dra7xx_2D00_evm_2D00_dsp_2D00_c6x_2D00_noos.cmm

0 Gerardo Artola Pola1 over 3 years ago in reply to Richard Woodruff

Prodigy 70 points

Hi Richard,

good news, I've got it working. The problem was the DSP firmware (based on openCL + Ti IPC). The firmware was sending the dsp to idle. Once I got to load a dummy DSP firmware by remoteproc, without the "idle part", all the problems were solved.

Now the JTAG can control properly the CA15 (Linux aware) and both DSPs (SYSBIOS aware).

Thank you a lot for your help. All the brainstorming power was good and needed to solve this one :)

BR,

Gerardo

0 Richard Woodruff over 3 years ago in reply to Gerardo Artola Pola1

TI__Genius 17575 points

Hello Gerardo,

Glad to hear it is working. Thanks for feeding back the resolution. With that good connection, a lot of tools are now available. I often use processor trace into the onchip memory (32K) for both the DSP and the A15s. Often many mS of execution can be captured.. Since the buffer is somewhat small usually I run them exclusively to limit overflows. If you have an EVM with the external EMU pins exposed then offchip can be used to a huge receiver. This will give many tens of seconds more/less depending on the receiver size (1GB to 4GB).

Regards,

Richard W.

Processors

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PROCESSOR-SDK-DRA7X: Multiprocessor debugging under Linux embedded