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Part Number: TDA4VMXEVM
Hello,
We would like to switch our custom node to another target IPU (e.g. IPU1_1) for performance boost.
Is this supported in our TDA4 PSDK implementation and how can it be achieved?
Some information about the software:
- PSDK version is PSDK_06_02_00_21.
Regards,
Todor
Hi Karan,
Yes, the node is an OpenVx node. In the example vision_apps basic demos IPU1_0 (TIVX_TARGET_IPU1_0) is used for the aewb node. As far as I know this TIVX_TARGET_IPU1_0 is MAIN_Cortex_R5_0_1 (mcu2_1). We would like to run our custom node on any other R5F core.
Regards,
Todor
Todor,
Is this your AEWB algorithm or are you using TI AEWB?
In any case, if the node is registered for a specific core, it could be run on that core.. So you need to register your AEWB node for other R5F code and then in the application, you could set the target on which you want to run AEWB?
Btw, what is the R5F load that you are seeing with AEWB? Essentially what's the performance you are seeing?
Regards,
Brijesh
Hi Brijesh,
It is not the default TI AEWB but our custom AEWB implementation.
I tried registering the node for the TIVX_TARGET_IPU1_1 core but after running the performance command it would report that the node was still running on IPU1-0 and there was no change in the performance. The target is registered in the use case and in the kernel part.
In this file: tiovx/source/platform/psdk_j7/common/tivx_platform_psdk_j7.h
there are no included settings for TIVX_TARGET_IPU1_1. Perhaps this specific target is not supported?
ln 79:
ln 145:
These are the build flags in vision_apps:
# Build specific CPUs
BUILD_CPU_MPU1?=yes
BUILD_CPU_MCU1_0?=no
BUILD_CPU_MCU2_0?=no
BUILD_CPU_MCU2_1?=yes
BUILD_CPU_MCU3_0?=no
BUILD_CPU_MCU3_1?=no
BUILD_CPU_C6x_1?=yes
BUILD_CPU_C6x_2?=yes
BUILD_CPU_C7x_1?=yes
Are there any modifications needed in the build system?
Occasionally we are observing performance drops in specific use cases and our opinion is that it would be optimal to move the custom node to another core (similar to TDA3).
Regards,
Todor
Hello Todor,
There is an existing issue in the 6.2 SDK causing performance drops when using the AEWB node to send AEWB params to the VISS via a delay object to the AEWB node. This issue will be fixed in the 7.0 SDK by sending the AEWB params directly from the AEWB to the VISS node via a remote service API. Do you have the performance requirements of your AEWB algorithm to see if this can fit on the current MCU2_1 with this change?
In the meantime, you can instead make the AEWB params a graph parameter within the application and enqueue the params from the AEWB node directly to the VISS node and therefore avoid the issues caused by the delay object.
If you require the AEWB node to be moved to the MCU2_0, this will be a more involved change that is untested from TI's side. Therefore it may require some trial and error to get this working. If this is the route that you prefer, we can provide suggestions of how to do so.
Regards,
Lucas
Hello Lucas,
In the past we had some performance drops while using the delay and had to switch to event based scheduling (enqueue/dequeue graph parameters).
We would prefer moving the AEWB node to the MCU2_0 to prevent any future performance drops on specific use-cases.
Your suggestions and support would be appreciated!
Regards,
Todor
Hello Todor,
The first change is to replace the line "#undef ENABLE_TIOVX" with "define ENABLE_TIOVX" in the file below:
vision_apps/apps/basic_demos/app_tirtos/common/app_cfg_mcu2_0.h
The next change is to modify the file below and add APP_IPC_CPU_MCU2_0 after APP_IPC_CPU_MCU2_1 in the g_ipc_cpu_id_map structure by replacing the existing entry which is APP_IPC_CPU_INVALID.
tiovx/source/platform/psdk_j7/common/tivx_ipc.c
Next, you will need to add the line "TIVX_TARGET_ID_IPU1_1 = TIVX_MAKE_TARGET_ID(TIVX_CPU_ID_IPU1_1, 0u)" to the tivx_target_id_e structure in the below file.
tiovx/source/platform/psdk_j7/common/tivx_platform_psdk_j7.h
Finally, you will then need to modify the functions tivxPlatformCreateTargets and tivxPlatformDeleteTargets in the file below. In these functions, you will need to call tivxGetSelfCpuId() to get an enum called "self_cpu". This will return either TIVX_CPU_ID_IPU1_0 or TIVX_CPU_ID_IPU1_1. You can then have an if/else to make the existing calls to tivxPlatformCreateTargetId/tivxPlatformDeleteTargetId if the self_cpu is equal to TIVX_CPU_ID_IPU1_0. Otherwise, you will call the tivxPlatformCreateTargetId/tivxPlatformDeleteTargetId with the TIVX_TARGET_ID_IPU1_0 as the first argument.
tiovx/source/platform/psdk_j7/bios/tivx_target_config_mcu2_1.c
For an example of the tivxGetSelfCpuId, please see tiovx/source/platform/psdk_j7/bios/tivx_target_config_dsp.c
Please give this a try and let me know if there are any issues you face.
Regards,
Lucas
Hi Lucas,
Thanks for the detailed explanation!
I applied the changes you described. There were two functions which could not be found during linking of vx_app_tirtos_linux_mcu2_0.out:
tivxRegisterSampleTargetR5FKernels and tivxUnRegisterSampleTargetR5FKernels, and this was fixed by adding this dependancy
STATIC_LIBS += vx_target_kernels_sample_r5f
to the following concerto file:
vision_apps/apps/basic_demos/app_tirtos/tirtos_linux/mcu2_0/concerto.mak
Then this error was thrown:
error: creating output section ".pcie_queue_shmem" without a SECTIONS
specification
Linking vision_apps/out/J7/R5F/SYSBIOS/release/vx_app_tirtos_linux_mcu2_0.out
error: errors encountered during linking;
"vision_apps/out/J7/R5F/SYSBIOS/debug/vx_app_tirtos_linux_mcu2_0.out" not built
concerto/finale.mak:206: recipe for target 'vision_apps/out/J7/R5F/SYSBIOS/debug/vx_app_tirtos_linux_mcu2_0.out' failed
make[1]: [vision_apps/out/J7/R5F/SYSBIOS/debug/vx_app_tirtos_linux_mcu2_0.out] Error 1 (ignored)
Building vx_app_tirtos_linux_mcu2_0.out as static library
Linking vision_apps/out/J7/R5F/SYSBIOS/release/vx_app_tirtos_linux_mcu2_1.out
error: creating output section ".pcie_queue_shmem" without a SECTIONS
specification
<Assembling>
<Assembling>
error: errors encountered during linking;
"vision_apps/out/J7/R5F/SYSBIOS/release/vx_app_tirtos_linux_mcu2_0.out" not built
Regards,
Todor
Hello Todor,
Can you try removing this section from the linker.cmd file? This is not needed for your application.
Regards,
Lucas
Hello Lucas,
I tried removing it from the linker.cmd file but the same error was thrown. Then I tried removing PCIE_QUEUE_SHARED_MEM and PCIE_QUEUE_MIRROR_REMOTE_SHARED_MEM from the linker_mem_map.cmd file but that did not resolve the error.
Regards,
Todor
Hello Todor,
Can you try doing a scrub build of vision_apps and see if this helps?
Regards,
Lucas
Hi Lucas,
I've been doing only scrub builds so far but it doesn't help.
Regards,
Todor
Hello Todor,
Can you attach the full log when you try to build vision apps?
Regards,
Lucas
Hello Todor,
If you are not using these kernels, can you remove the calls to tivxRegisterSampleTargetR5FKernels and tivxUnRegisterSampleTargetR5FKernels in vision_apps/apps/basic_demos/app_tirtos/common/app_init.c? If you modified vision_apps/apps/basic_demos/app_tirtos/tirtos_linux/mcu2_0/concerto.mak can you revert these changes as well?
I locally tested this and it built for me, so hopefully this works on your end as well.
Regards,
Lucas
Hello Lucas,
Thank you for the support!
After removing the calls to tivxRegisterSampleTargetR5FKernels and tivxUnRegisterSampleTargetR5FKernels and reverting the changes to the linker files - the build is successful.
When running the use case, the performance prints state that the node is running on IPU1-0, although it is set to run on TIVX_TARGET_IPU1_1 target in the use case.
In the kernel's host part this line has been added:
tivxAddKernelTarget(kernel, TIVX_TARGET_IPU1_1);
And this was added in the target part:
else if ( self_cpu == TIVX_CPU_ID_IPU1_1 )
{
strncpy(target_name, TIVX_TARGET_IPU1_1, TIVX_TARGET_MAX_NAME);
status = VX_SUCCESS;
}
Are any other changes required?
Regards,
Todor
Hello Todor,
So in the application code, are you calling vxSetNodeTarget to assign this node to the target TIVX_TARGET_IPU1_1?
If so, could you put a print statement inside the else if statement where the target kernel code is checking for the CPU ID of IPU1_1 and send me the log from running vision_apps_init.sh with this change?
Regards,
Lucas
Hello Lucas,
Yes, in the application code the target is set to TIVX_TARGET_IPU1_1.
I put print statements after the tivxGetSelfCpuId call and inside the else if statement. tivxGetSelfCpuId seems to return 6 and the code inside the else if statement is never reached.
The vision_apps_init log is attached.
APP_LOG: Mapping 0xac000000 ... APP_LOG: Mapped 0xac000000 -> 0xffffbc670000 of size 262144 bytes [MCU2_1] 0.000456 s: CIO: Init ... Done !!! [MCU2_1] 0.000520 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz> [MCU2_1] 0.000561 s: APP: Init ... !!! [MCU2_1] 0.000578 s: SCICLIENT: Init ... !!! [MCU2_1] 0.000661 s: SCICLIENT: DMSC FW version [19.12.1-v 19.12a (Terrific Lla] [MCU2_1] 0.000700 s: SCICLIENT: DMSC FW revision 0x13 [MCU2_1] 0.000723 s: SCICLIENT: DMSC FW ABI revision 2.9 [MCU2_1] 0.000745 s: SCICLIENT: Init ... Done !!! [MCU2_1] 0.000764 s: UDMA: Init ... !!! [MCU2_1] 0.001467 s: UDMA: Init ... Done !!! [MCU2_1] 0.001512 s: MEM: Init ... !!! [MCU2_1] 0.001583 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d2c00000 of size 16777216 bytes !!! [MCU2_1] 0.001637 s: MEM: Created heap (DDR_NON_CACHE_ME, id=5, flags=0x00000000) @ ce000000 of size 67108864 bytes !!! [MCU2_1] 0.001679 s: MEM: Init ... Done !!! [MCU2_1] 0.001695 s: IPC: Init ... !!! [MCU2_1] 0.001723 s: IPC: 5 CPUs participating in IPC !!! [MCU2_1] 0.001756 s: IPC: Waiting for HLOS to be ready ... !!! [MCU2_1] 11.410246 s: IPC: HLOS is ready !!! [MCU2_1] 11.415025 s: IPC: Init ... Done !!! [MCU2_1] 11.415087 s: APP: Syncing with 4 CPUs ... !!! [MCU2_1] 11.415123 s: APP: Syncing with 4 CPUs ... Done !!! [MCU2_1] 11.415150 s: REMOTE_SERVICE: Init ... !!! [MCU2_1] 11.416614 s: REMOTE_SERVICE: Init ... Done !!! [MCU2_1] 11.416687 s: FVID2: Init ... !!! [MCU2_1] 11.416771 s: FVID2: Init ... Done !!! [MCU2_1] 11.416818 s: DSS: Init ... !!! [MCU2_1] 11.416842 s: DSS: Display type is eDP !!! [MCU2_1] 11.416862 s: DSS: SoC init ... !!! [MCU2_1] 11.416880 s: SCICLIENT: Sciclient_pmSetModuleState module=152 state=2 [MCU2_1] 11.416977 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_1] 11.417016 s: SCICLIENT: Sciclient_pmSetModuleState module=297 state=2 [MCU2_1] 11.417585 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_1] 11.417618 s: SCICLIENT: Sciclient_pmSetModuleState module=151 state=2 [MCU2_1] 11.417982 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_1] 11.418016 s: SCICLIENT: Sciclient_pmSetModuleClkParent module=152 clk=9 parent=11 [MCU2_1] 11.418306 s: SCICLIENT: Sciclient_pmSetModuleClkParent success [MCU2_1] 11.418337 s: SCICLIENT: Sciclient_pmSetModuleClkParent module=152 clk=13 parent=18 [MCU2_1] 11.418537 s: SCICLIENT: Sciclient_pmSetModuleClkParent success [MCU2_1] 11.418569 s: SCICLIENT: Sciclient_pmSetModuleClkParent module=152 clk=1 parent=2 [MCU2_1] 11.418774 s: SCICLIENT: Sciclient_pmSetModuleClkParent success [MCU2_1] 11.418804 s: SCICLIENT: Sciclient_pmSetModuleClkFreq module=152 clk=1 freq=148500000 [MCU2_1] 11.421583 s: SCICLIENT: Sciclient_pmSetModuleClkFreq success [MCU2_1] 11.421616 s: SCICLIENT: Sciclient_pmModuleClkRequest module=152 clk=1 state=2 flag=0 [MCU2_1] 11.422068 s: SCICLIENT: Sciclient_pmModuleClkRequest success [MCU2_1] 11.422098 s: DSS: SoC init ... Done !!! [MCU2_1] 11.463116 s: DSS: Init ... Done !!! [MCU2_1] 11.463178 s: VHWA: Init ... !!! [MCU2_1] 11.463201 s: SCICLIENT: Sciclient_pmSetModuleState module=290 state=2 [MCU2_1] 11.463353 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_1] 11.463387 s: SCICLIENT: Sciclient_pmSetModuleState module=48 state=2 [MCU2_1] 11.463543 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_1] 11.463576 s: SCICLIENT: Sciclient_pmSetModuleState module=305 state=2 [MCU2_1] 11.463692 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_1] 11.463718 s: VHWA: DOF Init ... !!! [MCU2_1] 11.468469 s: VHWA: DOF Init ... Done !!! [MCU2_1] 11.468551 s: VHWA: LDC Init ... !!! [MCU2_1] 11.471150 s: VHWA: LDC Init ... Done !!! [MCU2_1] 11.471212 s: VHWA: MSC Init ... !!! [MCU2_1] 11.479057 s: VHWA: MSC Init ... Done !!! [MCU2_1] 11.479141 s: VHWA: NF Init ... !!! [MCU2_1] 11.480547 s: VHWA: NF Init ... Done !!! [MCU2_1] 11.480603 s: VHWA: SDE Init ... !!! [MCU2_1] 11.482609 s: VHWA: SDE Init ... Done !!! [MCU2_1] 11.482665 s: VHWA: VISS Init ... !!! [MCU2_1] 11.487995 s: VHWA: VISS Init ... Done !!! [MCU2_1] 11.488055 s: VHWA: VDEC Init ... !!! [MCU2_1] 11.502420 s: VHWA: VDEC Init ... Done !!! [MCU2_1] 11.502480 s: VHWA: VENC Init ... !!! [MCU2_1] 11.544684 s: VHWA: VENC Init ... Done !!! [MCU2_1] 11.544740 s: VHWA: Init ... Done !!! [MCU2_1] 11.544777 s: VX_ZONE_INIT:Enabled [MCU2_1] 11.544800 s: VX_ZONE_ERROR:Enabled [MCU2_1] 11.544819 s: VX_ZONE_WARNING:Enabled [MCU2_1] 11.547958 s: VX_ZONE_ERROR:[tivxTargetCreate:1260] tivxTargetCreate: target is NULL [MCU2_1] 11.548015 s: VX_ZONE_ERROR:[tivxPlatformCreateTargetId:55] Could not Add Target [MCU2_1] 11.548060 s: VX_ZONE_INIT:[tivxInit:64] Initialization Done !!! [MCU2_1] 11.548089 s: APP: OpenVX Target kernel init ... !!! [MCU2_1] 11.555280 s: >>SELF_CPU = 6 [MCU2_1] 11.555336 s: APP: OpenVX Target kernel init ... Done !!! [MCU2_1] 11.555365 s: CSI2RX: Init ... !!! [MCU2_1] 11.555383 s: SCICLIENT: Sciclient_pmSetModuleState module=25 state=2 [MCU2_1] 11.555476 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_1] 11.555512 s: SCICLIENT: Sciclient_pmSetModuleState module=26 state=2 [MCU2_1] 11.555692 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_1] 11.555723 s: SCICLIENT: Sciclient_pmSetModuleState module=27 state=2 [MCU2_1] 11.555861 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_1] 11.555892 s: SCICLIENT: Sciclient_pmSetModuleState module=147 state=2 [MCU2_1] 11.555982 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_1] 11.556012 s: SCICLIENT: Sciclient_pmSetModuleState module=148 state=2 [MCU2_1] 11.556105 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_1] 11.556693 s: CSI2RX: Init ... Done !!! [MCU2_1] 11.556744 s: CSI2TX: Init ... !!! [MCU2_1] 11.556766 s: SCICLIENT: Sciclient_pmSetModuleState module=25 state=2 [MCU2_1] 11.556849 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_1] 11.556880 s: SCICLIENT: Sciclient_pmSetModuleState module=28 state=2 [MCU2_1] 11.557022 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_1] 11.557055 s: SCICLIENT: Sciclient_pmSetModuleState module=296 state=2 [MCU2_1] 11.557165 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_1] 11.557614 s: CSI2TX: Init ... Done !!! [MCU2_1] 11.557662 s: ISS: Init ... !!! [MCU2_1] 11.557723 s: Found sensor IMX390-UB953_D3 at location 0 [MCU2_1] 11.557814 s: Found sensor AR0233-UB953_MARS at location 1 [MCU2_1] 11.557865 s: Found sensor AR0820-UB953_LI at location 2 [MCU2_1] 11.557910 s: Found sensor IMX490-UB953_SONY at location 3 [MCU2_1] 11.557960 s: ISS: Init ... Done !!! [MCU2_1] 11.557986 s: UDMA Copy: Init ... !!! [MCU2_1] 11.559327 s: UDMA Copy: Init ... Done !!! [MCU2_1] 11.559398 s: APP: Init ... Done !!! [MCU2_1] 11.559423 s: APP: Run ... !!! [MCU2_1] 11.559441 s: IPC: Starting echo test ... [MCU2_1] 11.561690 s: APP: Run ... Done !!! [MCU2_1] 11.562995 s: IPC: Echo status: mpu1_0[x] mcu2_1[s] C66X_1[P] C66X_2[.] C7X_1[.] [MCU2_1] 11.563097 s: IPC: Echo status: mpu1_0[x] mcu2_1[s] C66X_1[P] C66X_2[P] C7X_1[.] [MCU2_1] 11.563170 s: IPC: Echo status: mpu1_0[x] mcu2_1[s] C66X_1[P] C66X_2[P] C7X_1[P] [C6x_1 ] 0.000709 s: CIO: Init ... Done !!! [C6x_1 ] 0.000741 s: ### CPU Frequency <ORG = 1350000000 Hz>, <NEW = 1350000000 Hz> [C6x_1 ] 0.000754 s: APP: Init ... !!! [C6x_1 ] 0.000760 s: SCICLIENT: Init ... !!! [C6x_1 ] 0.000818 s: SCICLIENT: DMSC FW version [19.12.1-v 19.12a (Terrific Lla] [C6x_1 ] 0.000829 s: SCICLIENT: DMSC FW revision 0x13 [C6x_1 ] 0.000837 s: SCICLIENT: DMSC FW ABI revision 2.9 [C6x_1 ] 0.000845 s: SCICLIENT: Init ... Done !!! [C6x_1 ] 0.000853 s: UDMA: Init ... !!! [C6x_1 ] 0.001621 s: UDMA: Init ... Done !!! [C6x_1 ] 0.001639 s: MEM: Init ... !!! [C6x_1 ] 0.001650 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d4000000 of size 16777216 bytes !!! [C6x_1 ] 0.001666 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!! [C6x_1 ] 0.001680 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ d5000000 of size 50331648 bytes !!! [C6x_1 ] 0.001695 s: MEM: Init ... Done !!! [C6x_1 ] 0.001702 s: IPC: Init ... !!! [C6x_1 ] 0.001714 s: IPC: 5 CPUs participating in IPC !!! [C6x_1 ] 0.001726 s: IPC: Waiting for HLOS to be ready ... !!! [C6x_1 ] 10.368163 s: IPC: HLOS is ready !!! [C6x_1 ] 10.372104 s: IPC: Init ... Done !!! [C6x_1 ] 10.372146 s: APP: Syncing with 4 CPUs ... !!! [C6x_1 ] 11.349138 s: APP: Syncing with 4 CPUs ... Done !!! [C6x_1 ] 11.349154 s: REMOTE_SERVICE: Init ... !!! [C6x_1 ] 11.349725 s: REMOTE_SERVICE: Init ... Done !!! [C6x_1 ] 11.349765 s: VX_ZONE_INIT:Enabled [C6x_1 ] 11.349776 s: VX_ZONE_ERROR:Enabled [C6x_1 ] 11.349785 s: VX_ZONE_WARNING:Enabled [C6x_1 ] 11.350706 s: VX_ZONE_INIT:[tivxInit:64] Initialization Done !!! [C6x_1 ] 11.350727 s: APP: OpenVX Target kernel init ... !!! [C6x_1 ] 11.350966 s: APP: OpenVX Target kernel init ... Done !!! [C6x_1 ] 11.350985 s: UDMA Copy: Init ... !!! [C6x_1 ] 11.356304 s: UDMA Copy: Init ... Done !!! [C6x_1 ] 11.356320 s: APP: Init ... Done !!! [C6x_1 ] 11.356328 s: APP: Run ... !!! [C6x_1 ] 11.356337 s: IPC: Starting echo test ... [C6x_1 ] 11.357332 s: APP: Run ... Done !!! [C6x_1 ] 11.357655 s: IPC: Echo status: mpu1_0[x] mcu2_1[x] C66X_1[s] C66X_2[x] C7X_1[P] [C6x_1 ] 11.358016 s: IPC: Echo status: mpu1_0[x] mcu2_1[x] C66X_1[s] C66X_2[P] C7X_1[P] [C6x_1 ] 11.496775 s: IPC: Echo status: mpu1_0[x] mcu2_1[P] C66X_1[s] C66X_2[P] C7X_1[P] [C6x_2 ] 0.000726 s: CIO: Init ... Done !!! [C6x_2 ] 0.000759 s: ### CPU Frequency <ORG = 1350000000 Hz>, <NEW = 1350000000 Hz> [C6x_2 ] 0.000772 s: APP: Init ... !!! [C6x_2 ] 0.000779 s: SCICLIENT: Init ... !!! [C6x_2 ] 0.000836 s: SCICLIENT: DMSC FW version [19.12.1-v 19.12a (Terrific Lla] [C6x_2 ] 0.000847 s: SCICLIENT: DMSC FW revision 0x13 [C6x_2 ] 0.000855 s: SCICLIENT: DMSC FW ABI revision 2.9 [C6x_2 ] 0.000865 s: SCICLIENT: Init ... Done !!! [C6x_2 ] 0.000873 s: UDMA: Init ... !!! [C6x_2 ] 0.001665 s: UDMA: Init ... Done !!! [C6x_2 ] 0.001684 s: MEM: Init ... !!! [C6x_2 ] 0.001696 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d8000000 of size 16777216 bytes !!! [C6x_2 ] 0.001712 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!! [C6x_2 ] 0.001726 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ d9000000 of size 50331648 bytes !!! [C6x_2 ] 0.001742 s: MEM: Init ... Done !!! [C6x_2 ] 0.001750 s: IPC: Init ... !!! [C6x_2 ] 0.001772 s: IPC: 5 CPUs participating in IPC !!! [C6x_2 ] 0.001785 s: IPC: Waiting for HLOS to be ready ... !!! [C6x_2 ] 10.591607 s: IPC: HLOS is ready !!! [C6x_2 ] 10.595336 s: IPC: Init ... Done !!! [C6x_2 ] 10.595379 s: APP: Syncing with 4 CPUs ... !!! [C6x_2 ] 11.302291 s: APP: Syncing with 4 CPUs ... Done !!! [C6x_2 ] 11.302307 s: REMOTE_SERVICE: Init ... !!! [C6x_2 ] 11.302890 s: REMOTE_SERVICE: Init ... Done !!! [C6x_2 ] 11.302930 s: VX_ZONE_INIT:Enabled [C6x_2 ] 11.302940 s: VX_ZONE_ERROR:Enabled [C6x_2 ] 11.302952 s: VX_ZONE_WARNING:Enabled [C6x_2 ] 11.303859 s: VX_ZONE_INIT:[tivxInit:64] Initialization Done !!! [C6x_2 ] 11.303880 s: APP: OpenVX Target kernel init ... !!! [C6x_2 ] 11.304126 s: APP: OpenVX Target kernel init ... Done !!! [C6x_2 ] 11.304150 s: UDMA Copy: Init ... !!! [C6x_2 ] 11.309682 s: UDMA Copy: Init ... Done !!! [C6x_2 ] 11.309702 s: APP: Init ... Done !!! [C6x_2 ] 11.309710 s: APP: Run ... !!! [C6x_2 ] 11.309718 s: IPC: Starting echo test ... [C6x_2 ] 11.310837 s: APP: Run ... Done !!! [C6x_2 ] 11.311176 s: IPC: Echo status: mpu1_0[x] mcu2_1[x] C66X_1[P] C66X_2[s] C7X_1[.] [C6x_2 ] 11.311209 s: IPC: Echo status: mpu1_0[x] mcu2_1[x] C66X_1[P] C66X_2[s] C7X_1[P] [C6x_2 ] 11.449955 s: IPC: Echo status: mpu1_0[x] mcu2_1[P] C66X_1[P] C66X_2[s] C7X_1[P] [C7x_1 ] 0.011571 s: CIO: Init ... Done !!! [C7x_1 ] 0.011593 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz> [C7x_1 ] 0.011609 s: APP: Init ... !!! [C7x_1 ] 0.011617 s: SCICLIENT: Init ... !!! [C7x_1 ] 0.011678 s: SCICLIENT: DMSC FW version [19.12.1-v 19.12a (Terrific Lla] [C7x_1 ] 0.011691 s: SCICLIENT: DMSC FW revision 0x13 [C7x_1 ] 0.011701 s: SCICLIENT: DMSC FW ABI revision 2.9 [C7x_1 ] 0.011711 s: SCICLIENT: Init ... Done !!! [C7x_1 ] 0.011719 s: UDMA: Init ... !!! [C7x_1 ] 0.011842 s: UDMA: Init ... Done !!! [C7x_1 ] 0.011853 s: MEM: Init ... !!! [C7x_1 ] 0.011864 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ dc000000 of size 469762048 bytes !!! [C7x_1 ] 0.011884 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 70020000 of size 8159232 bytes !!! [C7x_1 ] 0.011902 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 64800000 of size 491520 bytes !!! [C7x_1 ] 0.011919 s: MEM: Created heap (L1_MEM, id=3, flags=0x00000001) @ 64e00000 of size 16384 bytes !!! [C7x_1 ] 0.011936 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ f8000000 of size 67108864 bytes !!! [C7x_1 ] 0.011954 s: MEM: Init ... Done !!! [C7x_1 ] 0.011962 s: IPC: Init ... !!! [C7x_1 ] 0.011972 s: IPC: 5 CPUs participating in IPC !!! [C7x_1 ] 0.011985 s: IPC: Waiting for HLOS to be ready ... !!! [C7x_1 ] 10.666467 s: IPC: HLOS is ready !!! [C7x_1 ] 10.668571 s: IPC: Init ... Done !!! [C7x_1 ] 10.668585 s: APP: Syncing with 4 CPUs ... !!! [C7x_1 ] 11.243766 s: APP: Syncing with 4 CPUs ... Done !!! [C7x_1 ] 11.243784 s: REMOTE_SERVICE: Init ... !!! [C7x_1 ] 11.244026 s: REMOTE_SERVICE: Init ... Done !!! [C7x_1 ] 11.244047 s: VX_ZONE_INIT:Enabled [C7x_1 ] 11.244058 s: VX_ZONE_ERROR:Enabled [C7x_1 ] 11.244094 s: VX_ZONE_WARNING:Enabled [C7x_1 ] 11.244312 s: VX_ZONE_INIT:[tivxInit:64] Initialization Done !!! [C7x_1 ] 11.244326 s: APP: OpenVX Target kernel init ... !!! [C7x_1 ] 11.244401 s: APP: OpenVX Target kernel init ... Done !!! [C7x_1 ] 11.244415 s: APP: Init ... Done !!! [C7x_1 ] 11.244425 s: APP: Run ... !!! [C7x_1 ] 11.244433 s: IPC: Starting echo test ... [C7x_1 ] 11.244852 s: APP: Run ... Done !!! [C7x_1 ] 11.252297 s: IPC: Echo status: mpu1_0[x] mcu2_1[x] C66X_1[P] C66X_2[x] C7X_1[s] [C7x_1 ] 11.252649 s: IPC: Echo status: mpu1_0[x] mcu2_1[x] C66X_1[P] C66X_2[P] C7X_1[s] [C7x_1 ] 11.391455 s: IPC: Echo status: mpu1_0[x] mcu2_1[P] C66X_1[P] C66X_2[P] C7X_1[s]
Hello Todor,
Could you please uncomment ENABLE_IPC_MCU2_0 in the file vision_apps/apps/basic_demos/app_tirtos/common/app_cfg.h, rebuild and provide the log with this change?
Regards,
Lucas
Hello Lucas,
With the suggested change the code inside the else if statement is reached.
A log with the change is attached.
APP_LOG: Mapping 0xac000000 ... APP_LOG: Mapped 0xac000000 -> 0xffffa1780000 of size 262144 bytes [MCU2_0] 0.000440 s: CIO: Init ... Done !!! [MCU2_0] 0.000508 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz> [MCU2_0] 0.000551 s: APP: Init ... !!! [MCU2_0] 0.000568 s: SCICLIENT: Init ... !!! [MCU2_0] 0.000650 s: SCICLIENT: DMSC FW version [19.12.1-v 19.12a (Terrific Lla] [MCU2_0] 0.000686 s: SCICLIENT: DMSC FW revision 0x13 [MCU2_0] 0.000708 s: SCICLIENT: DMSC FW ABI revision 2.9 [MCU2_0] 0.000729 s: SCICLIENT: Init ... Done !!! [MCU2_0] 0.000749 s: MEM: Init ... !!! [MCU2_0] 0.000776 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d2800000 of size 4194304 bytes !!! [MCU2_0] 0.000823 s: MEM: Init ... Done !!! [MCU2_0] 0.000842 s: IPC: Init ... !!! [MCU2_0] 0.000868 s: IPC: 6 CPUs participating in IPC !!! [MCU2_0] 0.000898 s: IPC: Waiting for HLOS to be ready ... !!! [MCU2_0] 15.071612 s: IPC: HLOS is ready !!! [MCU2_0] 15.077037 s: IPC: Init ... Done !!! [MCU2_0] 15.077097 s: APP: Syncing with 5 CPUs ... !!! [MCU2_0] 15.363691 s: APP: Syncing with 5 CPUs ... Done !!! [MCU2_0] 15.363897 s: REMOTE_SERVICE: Init ... !!! [MCU2_0] 15.365541 s: REMOTE_SERVICE: Init ... Done !!! [MCU2_0] 15.365631 s: VX_ZONE_INIT:Enabled [MCU2_0] 15.365664 s: VX_ZONE_ERROR:Enabled [MCU2_0] 15.365686 s: VX_ZONE_WARNING:Enabled [MCU2_0] 15.368606 s: VX_ZONE_INIT:[tivxInit:64] Initialization Done !!! [MCU2_0] 15.368648 s: APP: OpenVX Target kernel init ... !!! [MCU2_0] 15.368733 s: >>SELF_CPU = 7 [MCU2_0] 15.368769 s: >>TIVXIPU1_1 SELF_CPU = 7 [MCU2_0] 15.368810 s: APP: OpenVX Target kernel init ... Done !!! [MCU2_0] 15.368839 s: APP: Init ... Done !!! [MCU2_0] 15.368859 s: APP: Run ... !!! [MCU2_0] 15.368876 s: IPC: Starting echo test ... [MCU2_0] 15.370907 s: APP: Run ... Done !!! [MCU2_0] 15.371667 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[x] C66X_1[x] C66X_2[x] C7X_1[P] [MCU2_0] 15.373204 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[x] C66X_1[P] C66X_2[x] C7X_1[P] [MCU2_1] 0.000469 s: CIO: Init ... Done !!! [MCU2_1] 0.000537 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz> [MCU2_1] 0.000577 s: APP: Init ... !!! [MCU2_1] 0.000593 s: SCICLIENT: Init ... !!! [MCU2_1] 0.000675 s: SCICLIENT: DMSC FW version [19.12.1-v 19.12a (Terrific Lla] [MCU2_1] 0.000714 s: SCICLIENT: DMSC FW revision 0x13 [MCU2_1] 0.000739 s: SCICLIENT: DMSC FW ABI revision 2.9 [MCU2_1] 0.000762 s: SCICLIENT: Init ... Done !!! [MCU2_1] 0.000782 s: UDMA: Init ... !!! [MCU2_1] 0.001487 s: UDMA: Init ... Done !!! [MCU2_1] 0.001534 s: MEM: Init ... !!! [MCU2_1] 0.001609 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d2c00000 of size 16777216 bytes !!! [MCU2_1] 0.001664 s: MEM: Created heap (DDR_NON_CACHE_ME, id=5, flags=0x00000000) @ ce000000 of size 67108864 bytes !!! [MCU2_1] 0.001708 s: MEM: Init ... Done !!! [MCU2_1] 0.001726 s: IPC: Init ... !!! [MCU2_1] 0.001754 s: IPC: 6 CPUs participating in IPC !!! [MCU2_1] 0.001789 s: IPC: Waiting for HLOS to be ready ... !!! [MCU2_1] 11.764622 s: IPC: HLOS is ready !!! [MCU2_1] 11.770171 s: IPC: Init ... Done !!! [MCU2_1] 11.770239 s: APP: Syncing with 5 CPUs ... !!! [MCU2_1] 11.770275 s: APP: Syncing with 5 CPUs ... Done !!! [MCU2_1] 11.770303 s: REMOTE_SERVICE: Init ... !!! [MCU2_1] 11.772198 s: REMOTE_SERVICE: Init ... Done !!! [MCU2_1] 11.772270 s: FVID2: Init ... !!! [MCU2_1] 11.772356 s: FVID2: Init ... Done !!! [MCU2_1] 11.772403 s: DSS: Init ... !!! [MCU2_1] 11.772422 s: DSS: Display type is eDP !!! [MCU2_1] 11.772443 s: DSS: SoC init ... !!! [MCU2_1] 11.772464 s: SCICLIENT: Sciclient_pmSetModuleState module=152 state=2 [MCU2_1] 11.772685 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_1] 11.772730 s: SCICLIENT: Sciclient_pmSetModuleState module=297 state=2 [MCU2_1] 11.773182 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_1] 11.773213 s: SCICLIENT: Sciclient_pmSetModuleState module=151 state=2 [MCU2_1] 11.773616 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_1] 11.773647 s: SCICLIENT: Sciclient_pmSetModuleClkParent module=152 clk=9 parent=11 [MCU2_1] 11.773875 s: SCICLIENT: Sciclient_pmSetModuleClkParent success [MCU2_1] 11.773913 s: SCICLIENT: Sciclient_pmSetModuleClkParent module=152 clk=13 parent=18 [MCU2_1] 11.774111 s: SCICLIENT: Sciclient_pmSetModuleClkParent success [MCU2_1] 11.774140 s: SCICLIENT: Sciclient_pmSetModuleClkParent module=152 clk=1 parent=2 [MCU2_1] 11.774354 s: SCICLIENT: Sciclient_pmSetModuleClkParent success [MCU2_1] 11.774382 s: SCICLIENT: Sciclient_pmSetModuleClkFreq module=152 clk=1 freq=148500000 [MCU2_1] 11.777287 s: SCICLIENT: Sciclient_pmSetModuleClkFreq success [MCU2_1] 11.777318 s: SCICLIENT: Sciclient_pmModuleClkRequest module=152 clk=1 state=2 flag=0 [MCU2_1] 11.777845 s: SCICLIENT: Sciclient_pmModuleClkRequest success [MCU2_1] 11.777888 s: DSS: SoC init ... Done !!! [MCU2_1] 11.818127 s: DSS: Init ... Done !!! [MCU2_1] 11.818192 s: VHWA: Init ... !!! [MCU2_1] 11.818216 s: SCICLIENT: Sciclient_pmSetModuleState module=290 state=2 [MCU2_1] 11.818383 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_1] 11.818417 s: SCICLIENT: Sciclient_pmSetModuleState module=48 state=2 [MCU2_1] 11.818588 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_1] 11.818621 s: SCICLIENT: Sciclient_pmSetModuleState module=305 state=2 [MCU2_1] 11.818737 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_1] 11.818767 s: VHWA: DOF Init ... !!! [MCU2_1] 11.823504 s: VHWA: DOF Init ... Done !!! [MCU2_1] 11.823583 s: VHWA: LDC Init ... !!! [MCU2_1] 11.826097 s: VHWA: LDC Init ... Done !!! [MCU2_1] 11.826157 s: VHWA: MSC Init ... !!! [MCU2_1] 11.833988 s: VHWA: MSC Init ... Done !!! [MCU2_1] 11.834048 s: VHWA: NF Init ... !!! [MCU2_1] 11.835433 s: VHWA: NF Init ... Done !!! [MCU2_1] 11.835485 s: VHWA: SDE Init ... !!! [MCU2_1] 11.837430 s: VHWA: SDE Init ... Done !!! [MCU2_1] 11.837482 s: VHWA: VISS Init ... !!! [MCU2_1] 11.842828 s: VHWA: VISS Init ... Done !!! [MCU2_1] 11.842894 s: VHWA: VDEC Init ... !!! [MCU2_1] 11.857358 s: VHWA: VDEC Init ... Done !!! [MCU2_1] 11.857420 s: VHWA: VENC Init ... !!! [MCU2_1] 11.901781 s: VHWA: VENC Init ... Done !!! [MCU2_1] 11.901837 s: VHWA: Init ... Done !!! [MCU2_1] 11.901874 s: VX_ZONE_INIT:Enabled [MCU2_1] 11.901896 s: VX_ZONE_ERROR:Enabled [MCU2_1] 11.901915 s: VX_ZONE_WARNING:Enabled [MCU2_1] 11.905136 s: VX_ZONE_ERROR:[tivxTargetCreate:1260] tivxTargetCreate: target is NULL [MCU2_1] 11.905197 s: VX_ZONE_ERROR:[tivxPlatformCreateTargetId:55] Could not Add Target [MCU2_1] 11.905244 s: VX_ZONE_INIT:[tivxInit:64] Initialization Done !!! [MCU2_1] 11.905272 s: APP: OpenVX Target kernel init ... !!! [MCU2_1] 11.912604 s: >>SELF_CPU = 6 [MCU2_1] 11.912662 s: APP: OpenVX Target kernel init ... Done !!! [MCU2_1] 11.912694 s: CSI2RX: Init ... !!! [MCU2_1] 11.912712 s: SCICLIENT: Sciclient_pmSetModuleState module=25 state=2 [MCU2_1] 11.912802 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_1] 11.912840 s: SCICLIENT: Sciclient_pmSetModuleState module=26 state=2 [MCU2_1] 11.912983 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_1] 11.913012 s: SCICLIENT: Sciclient_pmSetModuleState module=27 state=2 [MCU2_1] 11.913154 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_1] 11.913180 s: SCICLIENT: Sciclient_pmSetModuleState module=147 state=2 [MCU2_1] 11.913266 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_1] 11.913293 s: SCICLIENT: Sciclient_pmSetModuleState module=148 state=2 [MCU2_1] 11.913380 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_1] 11.913974 s: CSI2RX: Init ... Done !!! [MCU2_1] 11.914024 s: CSI2TX: Init ... !!! [MCU2_1] 11.914046 s: SCICLIENT: Sciclient_pmSetModuleState module=25 state=2 [MCU2_1] 11.914128 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_1] 11.914159 s: SCICLIENT: Sciclient_pmSetModuleState module=28 state=2 [MCU2_1] 11.914305 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_1] 11.914331 s: SCICLIENT: Sciclient_pmSetModuleState module=296 state=2 [MCU2_1] 11.914445 s: SCICLIENT: Sciclient_pmSetModuleState success [MCU2_1] 11.914913 s: CSI2TX: Init ... Done !!! [MCU2_1] 11.914959 s: ISS: Init ... !!! [MCU2_1] 11.915026 s: Found sensor IMX390-UB953_D3 at location 0 [MCU2_1] 11.915134 s: Found sensor AR0233-UB953_MARS at location 1 [MCU2_1] 11.915189 s: Found sensor AR0820-UB953_LI at location 2 [MCU2_1] 11.915237 s: Found sensor IMX490-UB953_SONY at location 3 [MCU2_1] 11.915294 s: ISS: Init ... Done !!! [MCU2_1] 11.915321 s: UDMA Copy: Init ... !!! [MCU2_1] 11.916712 s: UDMA Copy: Init ... Done !!! [MCU2_1] 11.916781 s: APP: Init ... Done !!! [MCU2_1] 11.916810 s: APP: Run ... !!! [MCU2_1] 11.916832 s: IPC: Starting echo test ... [MCU2_1] 11.919305 s: APP: Run ... Done !!! [MCU2_1] 11.920246 s: IPC: Echo status: mpu1_0[x] mcu2_0[.] mcu2_1[s] C66X_1[x] C66X_2[x] C7X_1[P] [MCU2_1] 11.920354 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[s] C66X_1[x] C66X_2[x] C7X_1[P] [C6x_1 ] 0.000707 s: CIO: Init ... Done !!! [C6x_1 ] 0.000738 s: ### CPU Frequency <ORG = 1350000000 Hz>, <NEW = 1350000000 Hz> [C6x_1 ] 0.000750 s: APP: Init ... !!! [C6x_1 ] 0.000756 s: SCICLIENT: Init ... !!! [C6x_1 ] 0.000813 s: SCICLIENT: DMSC FW version [19.12.1-v 19.12a (Terrific Lla] [C6x_1 ] 0.000824 s: SCICLIENT: DMSC FW revision 0x13 [C6x_1 ] 0.000832 s: SCICLIENT: DMSC FW ABI revision 2.9 [C6x_1 ] 0.000841 s: SCICLIENT: Init ... Done !!! [C6x_1 ] 0.000849 s: UDMA: Init ... !!! [C6x_1 ] 0.001618 s: UDMA: Init ... Done !!! [C6x_1 ] 0.001637 s: MEM: Init ... !!! [C6x_1 ] 0.001648 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d4000000 of size 16777216 bytes !!! [C6x_1 ] 0.001664 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!! [C6x_1 ] 0.001679 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ d5000000 of size 50331648 bytes !!! [C6x_1 ] 0.001694 s: MEM: Init ... Done !!! [C6x_1 ] 0.001701 s: IPC: Init ... !!! [C6x_1 ] 0.001713 s: IPC: 6 CPUs participating in IPC !!! [C6x_1 ] 0.001726 s: IPC: Waiting for HLOS to be ready ... !!! [C6x_1 ] 10.353295 s: IPC: HLOS is ready !!! [C6x_1 ] 10.357285 s: IPC: Init ... Done !!! [C6x_1 ] 10.357335 s: APP: Syncing with 5 CPUs ... !!! [C6x_1 ] 11.704076 s: APP: Syncing with 5 CPUs ... Done !!! [C6x_1 ] 11.704092 s: REMOTE_SERVICE: Init ... !!! [C6x_1 ] 11.704903 s: REMOTE_SERVICE: Init ... Done !!! [C6x_1 ] 11.704955 s: VX_ZONE_INIT:Enabled [C6x_1 ] 11.704968 s: VX_ZONE_ERROR:Enabled [C6x_1 ] 11.704978 s: VX_ZONE_WARNING:Enabled [C6x_1 ] 11.705931 s: VX_ZONE_INIT:[tivxInit:64] Initialization Done !!! [C6x_1 ] 11.705956 s: APP: OpenVX Target kernel init ... !!! [C6x_1 ] 11.706189 s: APP: OpenVX Target kernel init ... Done !!! [C6x_1 ] 11.706210 s: UDMA Copy: Init ... !!! [C6x_1 ] 11.711534 s: UDMA Copy: Init ... Done !!! [C6x_1 ] 11.711553 s: APP: Init ... Done !!! [C6x_1 ] 11.711603 s: APP: Run ... !!! [C6x_1 ] 11.711612 s: IPC: Starting echo test ... [C6x_1 ] 11.712833 s: APP: Run ... Done !!! [C6x_1 ] 11.713208 s: IPC: Echo status: mpu1_0[x] mcu2_0[.] mcu2_1[x] C66X_1[s] C66X_2[x] C7X_1[P] [C6x_1 ] 11.713412 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[x] C66X_1[s] C66X_2[x] C7X_1[P] [C6x_2 ] 0.000735 s: CIO: Init ... Done !!! [C6x_2 ] 0.000768 s: ### CPU Frequency <ORG = 1350000000 Hz>, <NEW = 1350000000 Hz> [C6x_2 ] 0.000781 s: APP: Init ... !!! [C6x_2 ] 0.000788 s: SCICLIENT: Init ... !!! [C6x_2 ] 0.000845 s: SCICLIENT: DMSC FW version [19.12.1-v 19.12a (Terrific Lla] [C6x_2 ] 0.000856 s: SCICLIENT: DMSC FW revision 0x13 [C6x_2 ] 0.000864 s: SCICLIENT: DMSC FW ABI revision 2.9 [C6x_2 ] 0.000874 s: SCICLIENT: Init ... Done !!! [C6x_2 ] 0.000882 s: UDMA: Init ... !!! [C6x_2 ] 0.001677 s: UDMA: Init ... Done !!! [C6x_2 ] 0.001696 s: MEM: Init ... !!! [C6x_2 ] 0.001708 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d8000000 of size 16777216 bytes !!! [C6x_2 ] 0.001724 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!! [C6x_2 ] 0.001739 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ d9000000 of size 50331648 bytes !!! [C6x_2 ] 0.001754 s: MEM: Init ... Done !!! [C6x_2 ] 0.001761 s: IPC: Init ... !!! [C6x_2 ] 0.001784 s: IPC: 6 CPUs participating in IPC !!! [C6x_2 ] 0.001797 s: IPC: Waiting for HLOS to be ready ... !!! [C6x_2 ] 10.462180 s: IPC: HLOS is ready !!! [C6x_2 ] 10.465984 s: IPC: Init ... Done !!! [C6x_2 ] 10.466019 s: APP: Syncing with 5 CPUs ... !!! [C6x_2 ] 11.658558 s: APP: Syncing with 5 CPUs ... Done !!! [C6x_2 ] 11.658575 s: REMOTE_SERVICE: Init ... !!! [C6x_2 ] 11.659398 s: REMOTE_SERVICE: Init ... Done !!! [C6x_2 ] 11.659456 s: VX_ZONE_INIT:Enabled [C6x_2 ] 11.659468 s: VX_ZONE_ERROR:Enabled [C6x_2 ] 11.659480 s: VX_ZONE_WARNING:Enabled [C6x_2 ] 11.660430 s: VX_ZONE_INIT:[tivxInit:64] Initialization Done !!! [C6x_2 ] 11.660454 s: APP: OpenVX Target kernel init ... !!! [C6x_2 ] 11.660698 s: APP: OpenVX Target kernel init ... Done !!! [C6x_2 ] 11.660722 s: UDMA Copy: Init ... !!! [C6x_2 ] 11.666329 s: UDMA Copy: Init ... Done !!! [C6x_2 ] 11.666351 s: APP: Init ... Done !!! [C6x_2 ] 11.666360 s: APP: Run ... !!! [C6x_2 ] 11.666369 s: IPC: Starting echo test ... [C6x_2 ] 11.667741 s: APP: Run ... Done !!! [C6x_2 ] 11.668046 s: IPC: Echo status: mpu1_0[x] mcu2_0[.] mcu2_1[x] C66X_1[x] C66X_2[s] C7X_1[P] [C6x_2 ] 11.668210 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[x] C66X_1[x] C66X_2[s] C7X_1[P] [C7x_1 ] 0.011578 s: CIO: Init ... Done !!! [C7x_1 ] 0.011601 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz> [C7x_1 ] 0.011618 s: APP: Init ... !!! [C7x_1 ] 0.011626 s: SCICLIENT: Init ... !!! [C7x_1 ] 0.011686 s: SCICLIENT: DMSC FW version [19.12.1-v 19.12a (Terrific Lla] [C7x_1 ] 0.011700 s: SCICLIENT: DMSC FW revision 0x13 [C7x_1 ] 0.011709 s: SCICLIENT: DMSC FW ABI revision 2.9 [C7x_1 ] 0.011719 s: SCICLIENT: Init ... Done !!! [C7x_1 ] 0.011728 s: UDMA: Init ... !!! [C7x_1 ] 0.011852 s: UDMA: Init ... Done !!! [C7x_1 ] 0.011863 s: MEM: Init ... !!! [C7x_1 ] 0.011874 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ dc000000 of size 469762048 bytes !!! [C7x_1 ] 0.011893 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 70020000 of size 8159232 bytes !!! [C7x_1 ] 0.011911 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 64800000 of size 491520 bytes !!! [C7x_1 ] 0.011928 s: MEM: Created heap (L1_MEM, id=3, flags=0x00000001) @ 64e00000 of size 16384 bytes !!! [C7x_1 ] 0.011944 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ f8000000 of size 67108864 bytes !!! [C7x_1 ] 0.011962 s: MEM: Init ... Done !!! [C7x_1 ] 0.011970 s: IPC: Init ... !!! [C7x_1 ] 0.011979 s: IPC: 6 CPUs participating in IPC !!! [C7x_1 ] 0.011991 s: IPC: Waiting for HLOS to be ready ... !!! [C7x_1 ] 10.671751 s: IPC: HLOS is ready !!! [C7x_1 ] 10.673936 s: IPC: Init ... Done !!! [C7x_1 ] 10.673949 s: APP: Syncing with 5 CPUs ... !!! [C7x_1 ] 11.600058 s: APP: Syncing with 5 CPUs ... Done !!! [C7x_1 ] 11.600076 s: REMOTE_SERVICE: Init ... !!! [C7x_1 ] 11.600352 s: REMOTE_SERVICE: Init ... Done !!! [C7x_1 ] 11.600378 s: VX_ZONE_INIT:Enabled [C7x_1 ] 11.600390 s: VX_ZONE_ERROR:Enabled [C7x_1 ] 11.600399 s: VX_ZONE_WARNING:Enabled [C7x_1 ] 11.600712 s: VX_ZONE_INIT:[tivxInit:64] Initialization Done !!! [C7x_1 ] 11.600730 s: APP: OpenVX Target kernel init ... !!! [C7x_1 ] 11.600808 s: APP: OpenVX Target kernel init ... Done !!! [C7x_1 ] 11.600824 s: APP: Init ... Done !!! [C7x_1 ] 11.600838 s: APP: Run ... !!! [C7x_1 ] 11.600846 s: IPC: Starting echo test ... [C7x_1 ] 11.601348 s: APP: Run ... Done !!! [C7x_1 ] 11.608021 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[x] C66X_1[x] C66X_2[x] C7X_1[s] [C7x_1 ] 11.609182 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[x] C66X_1[P] C66X_2[x] C7X_1[s]
Hello Todor,
Could you please send the full log from boot, including the log from the app?
Regards,
Lucas
Hello Todor,
Can you add a few debug print statements as shown below?
Please add a print inside the if statement at line 476 of tiovx/source/framework/vx_kernel.c to see if the num_targets = 0 and at line 487 of this file to see if the target string matched a string from the kernel target_name.
Please also add a print statement at line 161 of tiovx/source/platform/psdk_j7/bios/tivx_platform_bios.c to see if the target name matched one of the target names inside the g_tivx_platform_info struct.
Regards,
Lucas
Hello Lucas,
The full log is attached.
8737.full_log.log
>>MATCHED_PLATFORM_TARGET_NAME - corresponds to the print in tiovx/source/platform/psdk_j7/bios/tivx_platform_bios.c
>>MATCHED_STRING - corresponds to the print in tiovx/source/framework/vx_kernel.c: ln 487
The print at line 476 is never reached.
It seems that the platform target name IPU1-1 is never being matched.
Regards,
Todor
Hello Todor,
The line below seems to indicate that there is an issue with the registration of the IPU1_1 target, possibly to an incorrect name. Could you send me the files tiovx/source/platform/psdk_j7/bios/tivx_target_config_mcu2_1.c and tiovx/source/platform/psdk_j7/common/tivx_platform_sdk_j7.h for review?
[MCU2_0] 15.381509 s: >>MATCHED_PLATFORM_TARGET_NAME VPAC_MSC1
Hi Lucas,
The two files are attached.
tivx_platform_psdk_j7.h
/*
*******************************************************************************
*
* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
* ALL RIGHTS RESERVED
*
*******************************************************************************
*/
#include <vx_internal.h>
#include <tivx_platform_psdk_j7.h>
#define TIVX_TARGET_MCU2_1_MAX (17)
#define TIVX_TARGET_DEFAULT_STACK_SIZE (16U*1024U)
static void tivxPlatformCreateTargetId(vx_enum target_id, uint32_t i, const char *name);
static void tivxPlatformDeleteTargetId(vx_enum target_id);
/**
*******************************************************************************
* \brief Target Stack
*******************************************************************************
*/
static uint8_t gTarget_tskStack[TIVX_TARGET_MCU2_1_MAX][TIVX_TARGET_DEFAULT_STACK_SIZE]
__attribute__ ((section(".bss:taskStackSection")))
__attribute__ ((aligned(8192)))
;
static void tivxPlatformCreateTargetId(vx_enum target_id, uint32_t i, const char *name)
{
vx_status status;
tivx_target_create_params_t target_create_prms;
tivxTargetSetDefaultCreateParams(&target_create_prms);
target_create_prms.task_stack_ptr = gTarget_tskStack[i];
target_create_prms.task_stack_size = TIVX_TARGET_DEFAULT_STACK_SIZE;
target_create_prms.task_core_affinity = TIVX_TASK_AFFINITY_ANY;
target_create_prms.task_priority = 8U;
strncpy(target_create_prms.task_name, name,TIVX_TARGET_MAX_TASK_NAME);
target_create_prms.task_name[TIVX_TARGET_MAX_TASK_NAME-1U] = (char)0;
status = tivxTargetCreate(target_id, &target_create_prms);
if ((vx_status)VX_SUCCESS != status)
{
VX_PRINT(VX_ZONE_ERROR, "Could not Add Target\n");
}
}
static void tivxPlatformDeleteTargetId(vx_enum target_id)
{
vx_status status;
status = tivxTargetDelete(target_id);
if ((vx_status)VX_SUCCESS != status)
{
VX_PRINT(VX_ZONE_ERROR, "Could not Delete Target\n");
}
}
void tivxPlatformCreateTargets(void)
{
vx_enum self_cpu, target_id;
self_cpu = tivxGetSelfCpuId();
if ((vx_enum)TIVX_CPU_ID_IPU1_1 == self_cpu)
{
target_id = TIVX_TARGET_ID_IPU1_1;
} else
{
target_id = TIVX_TARGET_ID_IPU1_0;
}
tivxPlatformCreateTargetId(target_id, 0, "TIVX_CPU");
tivxPlatformCreateTargetId((vx_enum)TIVX_TARGET_ID_VPAC_NF, 1, "TIVX_NF");
tivxPlatformCreateTargetId((vx_enum)TIVX_TARGET_ID_VPAC_LDC1, 2, "TIVX_LDC1");
tivxPlatformCreateTargetId((vx_enum)TIVX_TARGET_ID_VPAC_MSC1, 3, "TIVX_MSC1");
tivxPlatformCreateTargetId((vx_enum)TIVX_TARGET_ID_VPAC_MSC2, 4, "TIVX_MSC2");
tivxPlatformCreateTargetId((vx_enum)TIVX_TARGET_ID_DMPAC_SDE, 5, "TIVX_SDE");
tivxPlatformCreateTargetId((vx_enum)TIVX_TARGET_ID_DMPAC_DOF, 6, "TIVX_DOF");
tivxPlatformCreateTargetId((vx_enum)TIVX_TARGET_ID_VPAC_VISS1, 7, "TIVX_VISS1");
tivxPlatformCreateTargetId((vx_enum)TIVX_TARGET_ID_CAPTURE1, 8, "TIVX_CAPT1");
tivxPlatformCreateTargetId((vx_enum)TIVX_TARGET_ID_CAPTURE2, 9, "TIVX_CAPT2");
tivxPlatformCreateTargetId((vx_enum)TIVX_TARGET_ID_DISPLAY1, 10, "TIVX_DISP1");
tivxPlatformCreateTargetId((vx_enum)TIVX_TARGET_ID_DISPLAY2, 11, "TIVX_DISP2");
tivxPlatformCreateTargetId((vx_enum)TIVX_TARGET_ID_VDEC1, 12, "TIVX_VDEC1");
tivxPlatformCreateTargetId((vx_enum)TIVX_TARGET_ID_VDEC2, 13, "TIVX_VDEC2");
tivxPlatformCreateTargetId((vx_enum)TIVX_TARGET_ID_VENC1, 14, "TIVX_VENC1");
tivxPlatformCreateTargetId((vx_enum)TIVX_TARGET_ID_VENC2, 15, "TIVX_VENC2");
tivxPlatformCreateTargetId((vx_enum)TIVX_TARGET_ID_CSITX, 16, "TIVX_CSITX");
}
void tivxPlatformDeleteTargets(void)
{
vx_enum self_cpu, target_id;
self_cpu = tivxGetSelfCpuId();
if ((vx_enum)TIVX_CPU_ID_IPU1_1 == self_cpu)
{
target_id = TIVX_TARGET_ID_IPU1_1;
} else
{
target_id = TIVX_TARGET_ID_IPU1_0;
}
tivxPlatformDeleteTargetId(target_id);
tivxPlatformDeleteTargetId((vx_enum)TIVX_TARGET_ID_VPAC_NF);
tivxPlatformDeleteTargetId((vx_enum)TIVX_TARGET_ID_VPAC_LDC1);
tivxPlatformDeleteTargetId((vx_enum)TIVX_TARGET_ID_VPAC_MSC1);
tivxPlatformDeleteTargetId((vx_enum)TIVX_TARGET_ID_VPAC_MSC2);
tivxPlatformDeleteTargetId((vx_enum)TIVX_TARGET_ID_DMPAC_SDE);
tivxPlatformDeleteTargetId((vx_enum)TIVX_TARGET_ID_DMPAC_DOF);
tivxPlatformDeleteTargetId((vx_enum)TIVX_TARGET_ID_VPAC_VISS1);
tivxPlatformDeleteTargetId((vx_enum)TIVX_TARGET_ID_CAPTURE1);
tivxPlatformDeleteTargetId((vx_enum)TIVX_TARGET_ID_CAPTURE2);
tivxPlatformDeleteTargetId((vx_enum)TIVX_TARGET_ID_DISPLAY1);
tivxPlatformDeleteTargetId((vx_enum)TIVX_TARGET_ID_DISPLAY2);
tivxPlatformDeleteTargetId((vx_enum)TIVX_TARGET_ID_VDEC1);
tivxPlatformDeleteTargetId((vx_enum)TIVX_TARGET_ID_VDEC2);
tivxPlatformDeleteTargetId((vx_enum)TIVX_TARGET_ID_VENC1);
tivxPlatformDeleteTargetId((vx_enum)TIVX_TARGET_ID_VENC2);
tivxPlatformDeleteTargetId((vx_enum)TIVX_TARGET_ID_CSITX);
}
Hello Todor,
Could you make the following changes?
1. In the tivx_platform_psdk_j7.h, could you add the following line to the #define TIVX_TARGET_INFO?
{TIVX_TARGET_IPU1_1, (vx_enum)TIVX_TARGET_ID_IPU1_1}, \
2. In tivx_target_config_mcu2_1.c, could you modify the logic inside the tivxPlatformCreateTargets and tivxPlatformDeleteTargets to only register the IPU1_1 target on MCU2_0 by doing the following in both files:
if ((vx_enum)TIVX_CPU_ID_IPU1_1 == self_cpu)
{
tivxPlatformCreateTargetId((vx_enum)TIVX_TARGET_ID_IPU1_1, 0, "TIVX_CPU");
} else
{
tivxPlatformCreateTargetId((vx_enum)TIVX_TARGET_ID_IPU1_0, 0, "TIVX_CPU");
tivxPlatformCreateTargetId((vx_enum)TIVX_TARGET_ID_VPAC_NF, 1, "TIVX_NF");
tivxPlatformCreateTargetId((vx_enum)TIVX_TARGET_ID_VPAC_LDC1, 2, "TIVX_LDC1");
tivxPlatformCreateTargetId((vx_enum)TIVX_TARGET_ID_VPAC_MSC1, 3, "TIVX_MSC1");
tivxPlatformCreateTargetId((vx_enum)TIVX_TARGET_ID_VPAC_MSC2, 4, "TIVX_MSC2");
tivxPlatformCreateTargetId((vx_enum)TIVX_TARGET_ID_DMPAC_SDE, 5, "TIVX_SDE");
tivxPlatformCreateTargetId((vx_enum)TIVX_TARGET_ID_DMPAC_DOF, 6, "TIVX_DOF");
tivxPlatformCreateTargetId((vx_enum)TIVX_TARGET_ID_VPAC_VISS1, 7, "TIVX_VISS1");
tivxPlatformCreateTargetId((vx_enum)TIVX_TARGET_ID_CAPTURE1, 8, "TIVX_CAPT1");
tivxPlatformCreateTargetId((vx_enum)TIVX_TARGET_ID_CAPTURE2, 9, "TIVX_CAPT2");
tivxPlatformCreateTargetId((vx_enum)TIVX_TARGET_ID_DISPLAY1, 10, "TIVX_DISP1");
tivxPlatformCreateTargetId((vx_enum)TIVX_TARGET_ID_DISPLAY2, 11, "TIVX_DISP2");
tivxPlatformCreateTargetId((vx_enum)TIVX_TARGET_ID_VDEC1, 12, "TIVX_VDEC1");
tivxPlatformCreateTargetId((vx_enum)TIVX_TARGET_ID_VDEC2, 13, "TIVX_VDEC2");
tivxPlatformCreateTargetId((vx_enum)TIVX_TARGET_ID_VENC1, 14, "TIVX_VENC1");
tivxPlatformCreateTargetId((vx_enum)TIVX_TARGET_ID_VENC2, 15, "TIVX_VENC2");
tivxPlatformCreateTargetId((vx_enum)TIVX_TARGET_ID_CSITX, 16, "TIVX_CSITX");
}
Regards,
Lucas
Hello Lucas,
The suggested changes resolved the issue - the node is currently running on MCU2_0.
Thank you for the support and the detailed explanations during the process!
P.S. Also the TIVX_PLATFORM_MAX_TARGETS in tiovx/source/platform/psdk_j7/common/tivx_platform_psdk_j7.h had to be increased with 1.
Regards,
Todor