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Original question:

eMMC Reset Line on am335x

AM3358: eMMC reset

Mark Mitchell
Intellectual 290 points
Part Number: AM3358

Hello -

We have been working with the beaglebone black and I have a related question.  the beaglebone uses gpio1_20 to reset the emmc as do we. I am trying to understand how this works.  Since at boot all of the boot code (except the lowest level boot code ) lives in the emmc so in order to get the gpio pin out of its default mode which is low at reset of the processor, at some point the low level boot code in the sitara rom must release the gpio pin allowing it to go high.  since the register setting for the gpios has not happened yet I am guessing  the low level boot rom code configures the pins to be inputs and thus floating so the reset line is pulled up by an external pullup on the reset pin.

can you confirm this is what happens and could you suggest why it wouold not be better to control the emmc with the system reset on the board instead?  

Thanks

Mark

  • 0
    Intellectual 290 points

    my apologies - upon closer inspection i see there is an inverter between the processor gpio pin and the emmc reset which means the gpio pin remains low out of reset which means the gpio pin is pulled low or driven low directly upon power on.  so this would mean to me that the only time the emmc could be put into reset at all would be the time between when power is applied and when processor power on reset completes which seems unrelaible to me. 

    I must be missing something here , please help.

    Thanks

    Mark

  • 0 in reply to Mark Mitchell
    TI__Guru 50741 points

    Hi Mark,

    a couple of notes:

    • The GPIO1_20 signal is not used by the ROM bootloader to reset the eMMC. You can see this in the "Initialization" chapter in the AM335x TRM, specifically by the absence of said signal in Table 26-27. Pins Used for MMC1 Boot.
    • The current U-Boot and Kernel also do not use this signal. I suppose it could be useful to recover from certain failure scenarios however the fact that it is not accessed at all makes me think that this is not really needed on AM335x devices. However this thread here points to an alternative reason for the connection to exist: https://e2e.ti.com/support/processors/f/791/t/362808

    Regards, Andreas

  • 0 in reply to Andreas Dannenberg
    Intellectual 290 points

    Hi Andreas

    thanks so much for the quick answer .  that is clear.

    so in light of this information does ti have a recommmendation as to how to handle the reset of the emmc devices in a system ? 

    Is the emmc pin expectedto be tied to system reset or to something else.  It looks to me that the emmc using the beaglebone scheme does not go through a well controlled reset at power on but rather depends on the power on profile of the power supplies in the specific system .  what I mean is that the only time the input to the inverter that drives the emmc reset pin ever goes high (may or may not) is for the period of time between 0 volts on the io lines of the sitara (no power ) and poweron reset ofthe sitara at which time the pin gpio1_26 (in this case) goes low.  It would also depend on the power on characteristics of the inverter gate.  this is waht I am calling not well controlled. 

    Please advise.

    thanks for your great help

    Mark

  • 0 in reply to Mark Mitchell
    TI__Guru 50741 points

    Hi Mark,

    Mark Mitchell said:
    so in light of this information does ti have a recommmendation as to how to handle the reset of the emmc devices in a system ? 

    I'd recommend to simply connect the eMMC reset signal together with the SOC's nRESETIN_OUT (active low Warm Reset) signal (might need to make sure voltage levels match). The reason is when you use eMMC in your system it is most likely your boot device, hence you want maximum reliability for this device to be ready and in working order during every boot. This implies that you probably want hardware to control the eMMC reset signal in some way. The SOC's nRESETIN_OUT pin gets also driven low by the SOC in situations such as watchdog timer timeouts, this way giving you a robust chance to reboot successfully no matter what happened to the eMMC controller state. If you were to control the eMMC reset signal via GPIO you would not able to easily do that in cases like a watchdog reset. The only use of a GPIO-controlled eMMC reset signal that I see would be if you need a way to improve the robustness of probing (or "reviving") the eMMC module in an already running system (that has already booted, at least partially). Doing some poking in both U-Boot and Kernel this doesn't appear something that is widely used (also you can't find really recommendations like "make sure you connect the eMMC reset signal to a GPIO!" anywhere online).

    Mark Mitchell said:
    t looks to me that the emmc using the beaglebone scheme does not go through a well controlled reset at power on but rather depends on the power on profile of the power supplies in the specific system .  what I mean is that the only time the input to the inverter that drives the emmc reset pin ever goes high (may or may not) is for the period of time between 0 volts on the io lines of the sitara (no power ) and poweron reset ofthe sitara at which time the pin gpio1_26 (in this case) goes low.  It would also depend on the power on characteristics of the inverter gate.  this is waht I am calling not well controlled. 

    I agree with this assessment. The circuit is not designed to provide a well-controlled reset for the eMMC device as part of the power-up sequence. At any rate, you would want a reset to happen each time the SOC resets for maximum robustness, hence my earlier recommendation.

    Also when you look at the newer designs such as the BeagleBone AI you see that the eMMC reset is actually tied directly into the system reset circuitry as well (schematic can be found here: https://github.com/beagleboard/beaglebone-ai)

    Regards, Andreas

  • 0 in reply to Andreas Dannenberg
    Intellectual 290 points

    Hello Andreas

    I have to say that this is by far the best answer I have received in a very long time.  I am blown away by your response, Complete , well thought out detailed and clearly researched.  You have well exceeded my expectations.  very well done.  I know what you are doing can be a thankless job so thanks very much.

    I think you are right in all points. I felt the same that the emmc is a pretty important part since everything arises from it in a sense.  I will implement the changes you suggest.

    I am sure the clarity of this answer will help many others browsing the forum for answers.


    Thanks again.

    Mark

  • 0 in reply to Mark Mitchell
    TI__Guru 50741 points

    Mark,

    Mark Mitchell said:
    I have to say that this is by far the best answer I have received in a very long time.  I am blown away by your response, Complete , well thought out detailed and clearly researched.  You have well exceeded my expectations.  very well done.  I know what you are doing can be a thankless job so thanks very much.

    thanks for the kind words. It is not exactly a thankless job (it pays my bills after all), but getting some feedback/confirmation about making an impact (but also how to possibly improve - we all can) is what keeps us as a team engaged and happy to help. We can only be successful when our customers are successful.

    Regards, Andreas