Part Number: PROCESSOR-SDK-DRA8X-TDA4X
Tool/software: Code Composer Studio
Hi :
i am using psdk_rtos_auto_j7_06_02_00_21 SDK
i import my cnn use tidl_model_import.out have some problem ,i do not know what to slove this !
follow is the log!
~/psdk_rtos_auto_j7_06_02_00_21/tidl_j7_01_01_00_10/ti_dl/utils/tidlModelImport$ ./out/tidl_model_import.out ../../../ti_dl/test/testvecs/config/import/public/caffe/tidl_import_landmark.txt
Caffe Network File : ../../test/testvecs/models/public/caffe/landmark/mouth_model_v6_rgb.prototxt
Caffe Model File : ../../test/testvecs/models/public/caffe/landmark/mouth_model_v6_rgb2.caffemodel
TIDL Network File : ../../test/testvecs/config/tidl_models/caffe/landmark/tidl_net_landmark.bin
TIDL IO Info File : ../../test/testvecs/config/tidl_models/caffe/landmark/tidl_io_landmark_
Name of the Network : resnet_128_40_v6
IPLayer,=128
WARNING: PReLU Layer fc256_relu's bias cannot be found(or not match) in coef file, Random bias will be generated! Only for evaluation usage! Results are all random!
IPLayer,=256
WARNING: PReLU Layer fc256_2_relu's bias cannot be found(or not match) in coef file, Random bias will be generated! Only for evaluation usage! Results are all random!
IPLayer,=80
~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~
Processing config file #0 : /home/super/psdk_rtos_auto_j7_06_02_00_21/tidl_j7_01_01_00_10/ti_dl/utils/tidlModelImport/tempDir/qunat_stats_config.txt
----------------------- TIDL Process with REF_ONLY FLOW ------------------------
# 0 . .. T 3.06 ... .... .....
# 1 . .. T 2.83 ... .... .....
------------------ Network Compiler Traces -----------------------------
Main iteration numer: 0....
Life time alive buffers are with ID: 10034 ( 0), 50033 ( 1), 60033 ( 1), 40002 ( 2), 20034 ( 0), 33 ( 2), 40001 ( 2),
Preparing for memory allocation : internal iteration number: 0
Mmeory overlap issue, dataId = 6, baseAddrconstSatisfied = -1
Main iteration numer: 1....
Life time alive buffers are with ID: 10034 ( 0), 50033 ( 1), 60033 ( 1), 40002 ( 2), 20034 ( 0), 33 ( 2), 40001 ( 2),
Preparing for memory allocation : internal iteration number: 0
successful Memory allocation
-------------------- Network Compiler : Analysis Results are available --------------------
****************************************************
** ALL MODEL CHECK PASSED **
****************************************************
Thanks!
Shuai