Part Number: TSW40RF80EVM
I have a TSW40RF80EVM board that connects to a TSW14J56EVM. I'm particularly interested in using the ADC to see a signal input at 430-MHz at around -20 dBm. I also use TSW40RF8x EVM GUI and High Speed Data Converter Pro software that I got from the website.
I was able to detect signals from as high as 1.96 GHz, but when I go below 940-MHz, I could not see the signal in the HSDC Pro software anymore. I'm wondering if you guys can help me configure both software to be able to detect at frequency of 430-MHz with an ADC Output Data Rate of at least greater than 1 Gsps.
And is there any way to configure the trigger functionality in the HSDC Pro software? Thanks!
In reply to Daniel Saspa:
The spurs are abnormal. Can you share the spectrum screenshot.
Are you locking the 122.88MHz VCXO on the TSW40RF80EVM with the signal generator. That could be the reason for the signal shift in HSDC pro.
The harmonics of the input signal will fold into the 1st nyquist and will appear at the ADC output. Is that what you're referring to? Are these in addition to the spurs which exist even without an input?
How are you clocking the ADC? is it through LMX or the DAC? Can you turn off the un-used clock.
There is a (more) detailed user's guide for the DAC and ADC used in this EVM available on our website. please feel free to review these.
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In reply to Satish Uppathil:
So we have to put in a 122.88 MHz signal into the J12 LMK clock input for it to work? Right now, we're using the LMX clock as our reference clock.
So for this inserted picture, we have an input of 1960 MHz into Channel A in bypass mode. We're expecting to see only the 1960 MHz signal but there are frequencies detected everywhere that interferes with the signal detection. Is there a way to remove those?
So what clock source for ADC are you referring to when we use the 10 MHz reference to J12? Is it LMK?
For the 82820 ini file, we are getting this error message. So the 82820 is not working for us right now. Is there an .ini file you can share with us so we can make 82820 work?
The clock source can be LMX or DAC and that will depend on the config file you choose to load. the jumper settings to route the DAC or LMX output as the ADC clk is also described in the UG.
The 82820 ini file should work. Check if the ref clock to the FPGA is active (probe the pins). Also, why have you set the ADC output data rate as 245.76M? this is bypass mode. You can use the ADC32RF45 UG as reference for more information on the bypass mode.
Thanks for answering my questions thus far. We are able to get a signal through bypass mode now. However, our goal is to be able to see two signals in an exact time frame to figure out latency in between. So our next goal is to see if we can trigger the data capture somehow.
I have questions about triggering:
1) How does the trigger functionality work? We keep seeing this Trigger option in the HSDC Pro menu but we could not figure out how to use it. Maybe you can shed more light into its algorithm for us.
2) Is there any possibility that we can get a trigger on an input signal routed through ADC Channel A or Channel B?
in the default case, HSDC pro starts the ADC output capture when you click the "capture" button in the GUI. So, the capture starts at an arbitrary point. The trigger option lets the user start the capture based on an external trigger. Trig in input in the TSWJ56 board can be used to start the ADC data capture in this case.
There's no option to trigger a capture based on an input into the ADC's input channel.
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