This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

  • TI Thinks Resolved

ADC32RF80: ADC32RF80

Prodigy 70 points

Replies: 1

Views: 536

Part Number: ADC32RF80

Hello!
I have custom board with two ADC32RF80 + LMK04828 + FPGA.
I run ADC on Fs = 2400 Mhz, Single-Band Complex Output, Decimation = 32, LMFS = 2441.
Both ADCs and FPGA clocked from one LMK (reference clocks and sysrefs).
Every ADC work fine, I see good samples. I have issue to synchronize data from two ADC. Both ADCs get same signal from generator. In FPGA I see skewed samples after JESD link (1-4 shifted samples).


Here are my steps to set up system:

1. Reset LMK over GPIO pin.
2. Initialization of LMK, SYSREF disabled.
3. Reset ADC over GPIO pin.
4. Initialization of ADC (I also setup the register 0x01E DDC DET LAT).
5. Initialization of JESD interface in FPGA.
6. Enable SYSREF as aperiodic multi-shot pulses (Datasheet page 33, 8.3.3.1 Using SYSREF):
     a) write to LMK SYSREF pulse command (1st SYSREF)
     b) delay > 40 us
     c) set MASK CLKDIV bit in ADC
     d) write to LMK SYSREF pulse command (2nd SYSREF)
     e) write to LMK SYSREF pulse command (3rd SYSREF)
     f) set MASK NCO and LMFC counter bit in ADC
    g) write to LMK SYSREF pulse command (4th SYSREF)

  • Hi,
    You may take a look at the following app note for some guidance on synchronization over JESD204B bus
    www.ti.com/.../slyt628.pdf

    Most of the constraints is on the FPGA capture side where the RBD (release buffer point) need to be optimized when capturing the two ADCs.
    If you have further questions you can reply back to this post and my colleague can take a further look.

    -Kang

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.