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CC2642 SPI write eeprom problem

hi professor,

software: ccs8.2  and  simplelink_cc26x2_sdk_2_30_00_34

In my design the cc2642 control eeprom by spi bus.I use the example named by spimaster_CC26X2R1_LAUNCHXL_tirtos_ccs to realize it. But I can only write ten data to eeprom at a time whatever the transaction.count is. As shown as following picture,I set the transaction.count is 20. Please give me some advice.

  • Hi Sunny, the humble professor here.

    What EEPROM you are trying to communicate with (part number, manufacturer)? When you are saying that you can only write 10-bytes, is this because you get an transaction error or is it based on some other observation?

    I would have a look at the EEPROM datasheet and ask myself the question "What do I expect to get back when writing these 20-bytes of data". Keep in mind that the SPI bus is full duplex.

    Best regards,

    M-W

  • In reply to M-W:

    hi M-W,
    The eeprom is M95512RDW6. I send 20-bytes of data to eeprom and when i read back, it just can read ten data which is right and another ten data are 0xFF. In the array named by spiCC26X2DMAHWAttrs I find the .minDmaTransferSize=10. But I set the parameter as 20, This is still the case.
  • In reply to Sunny:

    Hi Sunny,

    What are you communicating to the device? Have you double checked that the instruction and address you are sending to the device is correct for the operation you try to perform? In the code snippet above, you only show TX, not a TX/RX operation which would be expected in most cases.

    Regarding "minDmaTransferSize", this has nothing to do with the maximum number of bytes you can transfer. This variable marks the point where the driver will move from using a "polling" transfer mode to using the DMA.

    Best regards,

    M-W

  • In reply to M-W:

    hi M-W,
    The issue is resolved by set minDmaTransferSize value greater than the ready send data size. I do a experiment that I write 128-bytes data to eeprom and set minDmaTransferSize value 200, It's successful. But when I modify minDmaTransferSize value not exceeding 128-bytes. The issue occur.
  • In reply to Sunny:

    How are you implementing the chip select, are you using hardware or software controlled CS?

    The main difference between the two (assuming you use SW controlled CS) is timing, if it does not work when using DMA, then there might be a timing issue where some increased delay between each byte is enough to make it work.

    If you are using HW controlled CS (that is, the CS pin is assigned inside the spiCC26X2DMAHWAttrs table) then the behavior will be very different between the two modes as polling will toggle CS between each byte.

    I would recommend you to scope the SPI lines in both cases and see if there is any clear difference between polling and DMA and in how your EEPROM answers. It would be great if you could be provide traces of both scenarios.

    Best regards,

    M-W

  • In reply to M-W:

    hi M-W,
    I use the SW to control CS.In the spiCC26X2DMAHWAttrs table I assign CS pin as PIN_UNASSIGNED. I don't know the different between SW and HW for DMA and SPI bus.Do u have any description document ? I can try and provide traces of both scenarios.
  • In reply to Sunny:

    Hi Sunny,

    Let's see if you can get those traces produced and we can look at them. The difference when using SW CS should not be anything other then the timing in between the bytes.

    Best regards,

    M-W

  • In reply to M-W:

    hi M-W, 

        I wanner know when SPI_transfer() return value.

    When I assign the CS pin in spiCC26X2DMAHWAttrs table(use HW CS), I cannot read the eeprom data.As shown as the picture,it use SW CS. I redefine the pin at the HW CS.

  • In reply to Sunny:

    Hi Sunny,

    I would expect that to be the case as when you have HW CS and using polling mode (when ever you send less then minDmaTransferSize frames), the CS would toggle between every frame. When using SW, I guess you keep the signal low during the whole transaction.

    If you would use HW and DMA (lowering minDmaTransferSize to say 1), what is the outcome? In this case, the CS should stay low during the whole transaction.

    Ps, those logic traces had been great here as they would have showed the difference between SW and HW CS.

    Best regards,

    M-W