Part Number: AFE7685
I'm using AFE7685 in our project, since we are not using any eval board, we placed it on our own PCB. And according to the datasheet, we configure the syncb_cmos for our input and output syncb signal. Specifically, we are using syncb_cmos0 as input syncb and syncb_cmos1 as output syncb. At the mean time, we are using all 4T4R in our design, which means that we configured 4T to a single syncb pin and 4R to another syncb pin. However, when we started up the whole chip, we observed that the syncb_cmos1 (output syncb) cannot be pulled up after we reset the JESD state machine. And after that we modified our register configuration a little (enable only 4 SRXs instead of all 8 SRxs of serdes interface), the syncb_cmos1 can be pulled up. I don't know why this happen and is there any chance that we can use a single syncb output and all 8 SRXs?
Another question is about the datasheet, we want to perform a transport layer test at ADC side, which is related to the register 0x62~0x71 in page JESD_SERDES_TX. But I can't find the details of these registers. Where can we find the document for these registers?
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In reply to Kevin Zhu23:
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