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Part Number: ADS58J63

      ZYNQ ZCU102 FPGA ADC(ADS58J63) EVM bring up is facing interfacing issues. The LMFS 4841 mode 0 configuration file provided by TI  is not providing the required configuration. On loading the file in ADC GUI provided by TI, we are unable to obtain the option of setting  40x Mode, 4-Lanes/ADC as per our requirement under JESD PLL Mode drop-down menu in ADS54Jxx tab.
We tried manual configuration of ADC-JESD registers by creating a configuration file, according to the ADS58J63 user guide. On loading the same configuration file multiple times, we obtained different ADC outputs each time. Also, instead of getting bcbc... sequence as per K28.5 character set, we observed some other random sequence on each lane.
Kindly assist us in resolving this configuration issue. Looking forward to hearing from you.
PFA screenshots of ADS54Jxx GUI v1.8.