ADS58J63: Package electrical model of ADS58J63
Part Number: ADS58J63
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In reply to Ebenezer Dwobeng:
Hi Ebenezer Dwobeng, Cloud you help me ASAP. Any new revision document for ADS58J63 because I was found the modification done in the JESD PLL Mode. Could you share the Mode 0 LMFS 4841 configuration file for ADS58J63 EVM.
In reply to Vignesh ravi:
This is a quad channel device so there are 4 ADCs in each die. In LMF = 484 mode, each ADC uses 1 lane to transmit data as shown below.
4lanes/ADC will mean a total of 16lanes which is not supported by this device. After loading the config file for LMF=484 mode, you do not have to make any changes to the JESD204B interface in the GUI because the device will already be configured correctly
1) Yes, we also require one lane per ADC.
2)After uploading the Mode 0 config file, it does not shows LMFS 4841 option in JESD mode drop down menu in GUI as shown in figure.
3)Also, we require 40x mode,4lane/ADC but this option is not present in JESD PLL Mode drop down menu in GUI as shown in figure.
4)Select the device Tab is showing Incorrect part number.
5) After uploading Mode 0 config file without making any changes, following is the output we are receiving. As it can be seen, we are not obtaining bcbc.. sequence in any of the four lanes. bcbc.. sequence is requird by FPGA to assert JESD SYNC signal.
1) Already pressed the reset before dumping the config file in the board.
2)We are configuring the ADC board as per ADC EVM document. Still, we are not getting the bcbc.. sequence in any of the four lanes.
It is possible the ADC is expecting the JESD204B syncb on the syncbcd input so duplicate the same syncb from FPGA to syncbab and syncbcd input pins.
I expect the ADC to transmit BCBC characters when SYNCB is pulled low.
Kindly elaborate the steps to make SYNCB signal pulled low? And whether it should be done in hardware or software.
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