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TRF372017 power down control bits

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Replies: 2

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Questions about power down control bits (PWD_xxx) defined in Register 4 of TRF372017:

1. Can setting these bits achieve a more aggressive power saving mode than standard PS mode?

2. If yes, what is the power consumption when they are set?

3. Whether is SPI interface still active for communications when they are set?

4. What is the correct sequence to set them (power down)?

5. What is the correct sequence to clear them to wake up the modulator?  And how long does the modulator get settled to start transmit?

thanks,

  • Hi Hao,

    I hope you had a good weekend. I just wanted to let you know that I got your post and will make sure you get an answer soon, hopefully sometime this week.

    Thanks,

    Fern

  • In reply to Fern Yoon:

    Hi Hao,

    According to our product expert, each PLL block can be powered down individually by using the SPI registers. Combined with the PS (powersave) pin, this drops the 3.3V draw below 15mA. Measurements taken in the lab shows that it takes 200us to obtain frequency lock (100kHz) when restarting the PLL. I've attached a powerpoint that shows more detail of the PPL lock time measurement and the SPI register settings.

    7558.TRF3720_PG2P3 VCO_LockTime.pptx

    Thanks,

    Fern

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