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TRF372017 power down control bits

Other Parts Discussed in Thread: TRF372017

Questions about power down control bits (PWD_xxx) defined in Register 4 of TRF372017:

1. Can setting these bits achieve a more aggressive power saving mode than standard PS mode?

2. If yes, what is the power consumption when they are set?

3. Whether is SPI interface still active for communications when they are set?

4. What is the correct sequence to set them (power down)?

5. What is the correct sequence to clear them to wake up the modulator?  And how long does the modulator get settled to start transmit?

thanks,