ADC31RF80: SDO Problem

Part Number: ADC31RF80

Team,

Customer has issue to access digital SPI bank(analog SPI bank is OK) no matter to read 02h - 04h or to next 4 pages.  Would you please have a look below commends and let us know if any comments? Thanks.

ADC32RFxx_LOWLEVEL

0x0012 0x04    // write 4 to address 12 page select

0x0000 0x81    // software reset

0x0012 0x00

0x0011 0xFF    // write to address 0x0011 ADC page select

0x0022 0xC0  

0x0032 0x80   

0x0033 0x08   

0x0042 0x03   

0x0043 0x03   

0x0045 0x58   

0x0046 0xC4  

0x0047 0x01   

0x0053 0x01   

0x0054 0x08   

0x0064 0x05   

0x0072 0x84   

0x008C 0x80  

0x0097 0x80   

0x00F0 0x38   

0x00F1 0xBF   

0x0011 0x00    // Set 0x0011 with 0x00 to enable only master page later

0x0012 0x04    // write 4 to address 12 page select

0x0058 0x20     // SYNC polarity inverted as the hsdcpro.ini inverts the sync

0x0025 0x01    

0x0026 0x40

0x0027 0x80

0x0029 0x40

0x002A 0x80

0x002C 0x40

0x002D 0x80

0x002F 0x40

0x0034 0x01

0x003F 0x01

0x0039 0x50

0x003B 0x28

0x0040 0x80

0x0042 0x40

0x0043 0x80

0x0045 0x40

0x0046 0x80

0x0048 0x40

0x0049 0x80

0x004B 0x40

0x0053 0x60

0x0058 0x20    //Toggle inverse Sync to on (ini must also have isync = 1)

0x0059 0x02

0x005B 0x08

0x0062 0xE0

0x0065 0x81

0x0066 0x80    // increase JESD swing, 00 default, 80 max

0x006B 0x04     

0x006C 0x08

0x006E 0x80

0x006F 0xC0

0x0070 0xC0

0x0071 0x03

0x0076 0xA0

0x0077 0x0A

0x007D 0x41

0x0081 0x18

0x0084 0x55

0x008A 0x41

0x008E 0x18

0x005c 0x07

0x0012 0x00     //master select 0x00

0x0011 0xFF

0x0083 0x07

0x005C 0x01

0x0011 0x00

0x0012 0x00     //master select 0x00

0x5000 0x01     // DDC enable CHA

0x5001 0x05     // DDC by 12 CHA

0x5002 0x01     // Two bands CHA

0x5007 0x10     // LSB NCO1 1890 MHz CHA

0x5008 0xA4     // MSB NCO1 1890 Mhz

0x5009 0x00     // LSB NCO2 1.75Ghz

0x500A 0x00     // MSB NCO2

0x500B 0x85     // LSB NCO3 1.78Ghz

0x500C 0x9A     // MSB NCO3

0x500D 0x92     // DDC1 LSB NCO 1.99Ghz

0x500E 0x93     // DDC1 MSB NCO

0x5014 0x01     // 6dB DDC0

0x5016 0x01     // 6dB DDC1

0x5800 0x01     // DDC enable CHB

0x5801 0x05     // DDC by 12 CHB

0x5802 0x01     // Two bands CHB

0x5807 0x10     // LSB NCO1 1890 MHz CHB

0x5808 0xA4     // MSB NCO1 1890 Mhz

0x5809 0x00     // LSB NCO2 1.75Ghz

0x580A 0x00     // MSB NCO2

0x580B 0x85     // LSB NCO3 1.78Ghz

0x580C 0x9A     // MSB NCO3

0x580D 0xe8     // DDC1 LSB NCO 1.78Ghz

0x580E 0x97     // DDC1 MSB NCO

0x5814 0x01     // 6dB DDC0

0x5816 0x01     // 6dB DDC1

0x4001 0x00

0x4002 0x00

0x4003 0x00     //channel A

0x4004 0x68

0x6044 0x60       // Loop EN1

0x6068 0x40       // Loop EN2

0x60A2 0x09   // nyquist zone = 2

0x4003 0x01       // channelB

0x4004 0x68

0x6044 0x60       // Loop EN1

0x6068 0x40       // Loop EN2

0x60A2 0x09   // nyquist zone = 2

0x608D 0x50   // IMD3 correction

0x608B 0x05   // IMD3 correction

0x6000 0x00    //clear reset

0x7000 0x00

0x6000 0x01    //reset digital

0x7000 0x01

0x6000 0x00    //clear reset

0x7000 0x00

0x4003 0x00

0x4004 0x69

0x6002 0x01            // set JESD mode0 = 1

0x7002 0x01            // set JESD mode0 = 1

0x6037 0x00            // PLL MODE = 20x

0x7037 0x00            // PLL MODE = 20x

0x6032 0x3C           // set -6.2dB TX de-emphasis Lane 0, chA

0x7032 0x3C           // set -6.2dB TX de-emphasis Lane 1, chA

0x6033 0x3C           // set -6.2dB TX de-emphasis Lane 2, chA

0x7033 0x3C           // set -6.2dB TX de-emphasis Lane 3, chA

0x6034 0x3C           // set -6.2dB TX de-emphasis Lane 0, chB

0x7034 0x3C           // set -6.2dB TX de-emphasis Lane 1, chB

0x6035 0x3C           // set -6.2dB TX de-emphasis Lane 2, chB

0x7035 0x3C           // set -6.2dB TX de-emphasis Lane 3, chB

0x6001 0x80            //EN CTRL K

0x7001 0x80

0x6007 0x0F            //set K to 15

0x7007 0x0F

Regards,

Allan

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